618 326

1. 618 326 Physics of electronic materials and devices I Lecture 8

2. Thermionic emission process • It is the phenomenon that carriers having high energy thermionically emitted into the vacuum. • In other words, electrons escapes from the hot or high temperature surface of the material. • This is called “thermionic emission process”.

3. Thermionic emission process • Electron affinity q is the energy difference between the conduction band edge and the vacuum. • Work function q is the energy between the Fermi level and the vacuum level in the semiconductor.

4. Thermionic emission process • It is clearly seen that an electron can thermionically escape from the semiconductor surface into the vacuum if its energy is above q. • The electron density with energies above q can be found by where Vn is the difference between the bottom of the conduction band and the Fermi level.

5. Thermionic emission process • If escaping electrons with velocity normal to the surface and having energy greater than EF+ q, the thermionic current density is equal to

6. Thermionic emission process • Then we use p = mv and, and after integration, it yields

7. Example 1 • Calculate the thermionically emitted electron density nth at room temperature for an n-type silicon sample with an electron affinity q = 4.05 eV and qVn = 0.2 eV. If we reduce the effectiveq  to 0.6 eV, what is nth?

8. Example 1 • Soln • As we clearly see that at the room temperature, there is no thermionic emission of electrons into the vacuum. This thermionic emission process is important for metal-semiconductor contacts.

9. Tunneling Process • The figure shows the energy band when two semiconductor samples are brought close to each other. • The distance between them (d) is sufficient small, so that the electrons in the left-side semiconductor may transport across the barrier and move to the right-side semiconductor even the electron energy is much less than the barrier height. • This process is called “quantum tunneling process”.

10. Tunneling Process • The transmission coefficient can be expressed as • This process is used in tunnel diodes by having a small tunneling distance d, a low potential barrier qV0, and a small effective mass.

11. p-n Junction • A p-n junction plays a major role in electronic devices. • It is used in rectification, switching, and etc. • It is the simplest semiconductor devices. • Also, it is a key building block for other electronic, microwave, or photonic devices.

12. Basic fabrication steps The basic fabrication steps for p-n junction include • oxidation, • lithography, • diffusion or ion implanation, • and metallization.

13. Oxidation • This process is to make a high-quality silicon dioxide (SiO2) as an insulator in various devices or a barrier to diffusion or implanation during fabrication process. • There are two methods to grow SiO2: dry and wet oxidation, using dry oxygen and water vapor, respectively. • Generally, dry oxidation is used to form thin oxides because of its good Si-SiO2 interface characteristics, while wet oxidation is used for forming thicker layers since its higher growth rate.

14. Lithography • This process is called photolithography used to delineate the pattern of the p-n junction.

15. Lithography • (a) The wafer after the development. • (b) The wafer after SiO2 removal. • (c) The final result after a complete lithography process.

16. Diffusion and Ion Implantation • This is used to put the impurity into the semiconductor. • For diffusion method, the semiconductor surface not protected by the oxide is exposed to a high concentration of impurity. The impurity moves into the crystal by solid-state diffusion. • For the ion-implantation method, the impurity is introduced into the semiconductor by accelerating the impurity ions to a high-energy level and then implanting the ions in the semiconductor.

17. Metallization • This process is used to form ohmic contacts and interconnections. • After this process is done, the p-n junction is ready to use.

18. p-n junction rectification • The forward biased voltage is normally less than 1 V and the current increases rapidly as the biased voltage increases. • As the reverse bias increases, the current is still small until a breakdown voltage is reached, where the current suddenly increases.

19. Thermal equilibrium condition • Assume that both p- and n-type semiconductors are uniformly doped. • The Fermi level EF is near the valence band edge in the p-type material and near the conduction band edge in the n-type material.

20. Thermal equilibrium condition • Electrons diffuse from n-side toward p-side and holes diffuse from p-side toward n-side. • As electrons leave the n-side, they leave behind the positive donor ions (ND+) near the junction. • In the same way, some of negative acceptor ions (NA-) are left near the junction as holes move to the n-side.

21. Thermal equilibrium condition Space-charge region • The space-charge region is also called “depletion region” due to the depletion of free carriers. neutral neutral

22. Thermal equilibrium condition • Carrier diffusion induces an internal electric field in the opposite direction to free charge diffusion. • Therefore, the electron diffusion current flows from left to right, whereas the electron drift current flows from right to left.

23. Thermal equilibrium condition • At thermal equilibrium, the individual electron and hole current flowing across the junction are identically zero. • In the other words, the drift current cancels out precisely the diffusion current. Therefore, the equilibrium is reached as EFn = EFp.

24. Thermal equilibrium condition • The space-charge density distribution and the electrostatic potential  are given by Poisson’s equation as (1)

25. Thermal equilibrium condition • Assume that all donor and acceptor atoms are ionized. • Assume NA = 0 and n >> p for n-type neutral region and ND = 0 and p >> n for p-type neutral region.

26. Thermal equilibrium condition • The electrostatic potential  in of the n- and p-type with respect to the Fermi level can be found with the help of and as (2) (3)

27. Thermal equilibrium condition • The total electrostatic potential difference between the p-side and the n-side neutral region is called the “built-in potential” Vbi. It is written as (4)

28. p-n junction • a) A p-n junction with abrupt doping changes at the metallurgical junction. • (b) Energy band diagram of an abrupt junction at thermal equilibrium. • (c) Space charge distribution. • (d) Rectangular approximation of the space charge distribution.

29. Example 2 • Calculate the built-in potential for a silicon p-n junction with NA = 1018cm-3 and ND = 1015 cm-3 at 300 K. • Soln

30. Depletion Region The p-n junction may be classified into two classes depending on its impurity distribution: • the abrupt junction and • the linearly graded junction.

31. Abrupt junction • An abrupt junction can be seen in a p-n junction that is formed by shallow diffusion or low-energy ion implantation. • The impurity distribution in this case can be approximated by an abrupt transition of doping concentration between the n- and the p-type regions.

32. Linearly graded junction • In the linearly graded junction, the p-n junction may be formed by deep diffusions or high-energy ion implantations. • The impurity distribution varies linearly across the junction.

33. Abrupt Junction • Consider an abrupt junction as in the figure above, equation (1) can be written as (5)

34. Abrupt junction • The charge conservation is expressed by the condition Q = 0 or (6) To solve equation (5), we need to solve it separately for p-and n-type cases.

35. Abrupt junction

36. Abrupt junction (7)

37. Abrupt junction n-side: • Similarly, we can have (8) Let consider at x = 0 (9)

38. Abrupt junction • We may relate this electric field E to the potential over the depletion region as (10)

39. Abrupt junction • From (6), we have (11)

40. Abrupt junction • Substitute (11) into (10), this yields (12)

41. Abrupt junction • Hence, the space-charge layer width or depletion layer width can be written as (13)

42. Example 3 Si p-n diode of NA = 5 x 1016 cm-3 and ND = 1015 cm-3. Calculate (a) built-in voltage (b) depletion layer width (c) Em

43. Example 3 • Soln(a)

44. Example 3 • Soln(b)

45. Example 3 • Soln(c)

46. One-sided junction • If one side has much higher impurity doping concentration than another, i.e. NA >> ND or ND >> NA, then this is called “one-sided junction”. • Consider case of p+-n junction as in the figure (NA >> ND),

47. One-sided junction • Similarly, for n+-p junction of ND >> NA • The electric-field distribution could be written as where NB = lightly doped bulk concentration (i.e., NB = ND for p+-n junction)

48. Abrupt junction • The maximum electric field Em at x = 0 can be found as • Therefore, the electric-field distribution E(x) can be re-written as (16)

49. Abrupt junction • The potential distribution can be found from integrating (16) as (17)

50. Example 4 • For a silicon one-sided abrupt junction with NA = 1019cm-3 and ND = 1016 cm-3, calculate the depletion layer width and the maximum field at zero bias. • Soln