Memory Level Access

1. Memory Level Access October 22, 2007

2. Memory Level Access Status • Areas of Agreement • Standard CTL for Functional Operations • Timing is optional (point to STA Library) • Areas Needing Definition • Enumeration of Purposes for Macros • Scheduling and Compatibility of Operations • Complex Operations, e.g. Scan, Write Masks • Passive States and Power

3. Scheduling/Compatibility • Phenomena that must be described • Multiple Port Memories • Pipelined Memories • Data Corruption • Following is 2nd attempt at definition • New block inside PatternInformation • Existing CompatibilityInformation is too strictly targeted for complete patterns

4. Straw-Man Syntax PatternInformation { (Compatibility < Simultaneous | Offset NUM_CYCLES | Order > { (< (Macro (NAMED_MACRO)+ ;) | (Procedure (NAMED_PROCEDURE)+ ;) | (NotMacro (NAMED_MACRO)+ ;) | (NotProcedure (NAMED_PROCEDURE)+ ;) | (Result < Memory | Port PORT_NUM > < OldData | NewData | XMemory | XWord | XDifferences > ;) >)+ })+ }

5. Example (Partial Syntax) Environment { CTLMode mymode { DomainReferences { Procedures Memory_access; } PatternInformation { Procedure read_cycle_a { Purpose MemoryRead {Port 0} } Procedure write_cycle_a { Purpose MemoryWrite {Port 0} } Procedure read_cycle_b { Purpose MemoryRead {Port 1} } Procedure write_cycle_b { Purpose MemoryWrite {Port 1} } Procedure mem_bypass { Purpose Transparent; } Compatibility Simultaneous { Procedure write_cycle_a; Procedure read_cycle_b; Result Memory NewData; Result Port 1 OldData; } Compatibility Order { Procedure write_cycle_a write_cycle_b; NotProcedure mem_bypass; Procedure read_cycle_a read_cycle_b; Result Memory Xmemory; } } } }

6. Appendix (1/3) // This is a CTL fragment, showing just the memory access mechanism Signals { "test_clock" In; "addr"[9..0] In; "din"[31..0] In; "rwb" In; "csb" In; "oeb" In; "dout"[31..0] Out; } SignalGroups { "all_inputs" = '"test_clock" + "addr"[9..0] + "din"[31..0] + "rwb" + "csb" + "oeb"'; // 46 "all_outputs" = '"dout"[31..0]'; // 32 } Timing { WaveformTable "_default_WFT_" { Period '100ns'; Waveforms { "all_inputs" { 0 { '0ns' D; } } "all_inputs" { 1 { '0ns' 1; } } "all_inputs" { Z { '0ns' Z; } } "all_inputs" { N { '0ns' N; } } "all_outputs" { X { '0ns' X; '95ns' X; } } "all_outputs" { H { '0ns' X; '95ns' H; } } "all_outputs" { T { '0ns' X; '95ns' T; } } "all_outputs" { L { '0ns' X; '95ns' L; } } "test_clock" { P { '0ns' D; '45ns' U; '55ns' D; } } } } }

7. Appendix (2/3) Procedures Memory_access { "read_cycle" { W "_default_WFT_"; // C statement allows unimportant signals to be left undefined in V statements. C { "all_inputs" = 0 \45 N ; "all_outputs" = \32 X ; } V { “test_clock” = P; "rwb" = 1; "csb" = 0; "oeb" = 0; "addr"[7..0] = \8 # ; "dout"[31..0] = \32 # ; } } "write_cycle" { W "_default_WFT_"; C { "all_inputs" = 0 \45 N ; "all_outputs" = \32 X ; } V { “test_clock” = P; "rwb" = 0; "csb" = 0; "oeb" = 0; "addr"[7..0] = \8 # ; "din"[31..0] = \32 # ; } } }

8. Appendix (3/3) Environment { CTLMode mymode { DomainReferences { Procedures Memory_access; } PatternInformation { Procedure read_cycle { Purpose MemoryRead; } Procedure write_cycle { Purpose MemoryWrite; } } Internal { “test_clock” { DriveRequirements { TimingSensitive { Period Min ‘10ns’; Pulse High Min ‘5ns’; Pulse Low Min ‘5ns’; } } } “addr”[9..0] { DriveRequirements { TimingSensitive { Reference “test_clock” { ReferenceEdge Leading 1; Setup ‘2ns’; Hold ‘2ns’; } } } } // The other inputs would look similar “dout”[31..0] { StrobeRequirements { TimingSensitive { Reference “test_clock” { ReferenceEdge Leading 1; EarliestChange ‘1ns’; EarliestTimeValid ‘4ns’; } Reference “test_clock” { ReferenceEdge Leading 2; LatestTimeValid ‘0ns’; } } } } }}