Integration Challenges in Single-Chip Radios

1. Integration Challenges in Single-Chip Radios Adil Kidwai Intel Corporation, Hillsboro

2. Outline • Motivation – product targets • Architecture overview – Single-chip WiFi • Issues and Mitigation Techniques • Multi-standard coexistence in Single-chip • Issues and Mitigation techniques • Conclusions

3. Integration More Functionality Multi-Comm Double Sided Solution Why Integrate?Cost Pressure  Innovation Margins $ Time Need to push the BOM down ASP = Average Sales Price BOM = Bill of Material (Cost)

4. Why not to integrate? • Technology • It places extra dependence on RF design • To get to single-chip, the RF must migrate technologies at same pace as digital flow • Sku variation • How easy will it be to create different die for different markets and applications? • Multi-com becomes more complex to make silicon changes

5. RFIC FEM MAC RFIC Single chip defined (or not) Antennas FEM MAC • What is single-chip? • If you have a FEM, is it still single-chip? • How many devices should be combined to achieve the goal? What is the Goal?

6. Integration and Single-chip Ant 1 Ant 2

7. Specific ExampleSingle-chip WiFi – Top Down Design • Start with final board target • Determine expected BOM • Dive into package • Only then, into the silicon J.C.Jensen, A.A. Kidwai et al. RFIC 2010

8. Issues in single-chip radios • Package coupling • Board coupling • Silicon coupling • Thermal issues

9. Package Modeling • Modeling is important part of predicting, understanding, and mitigating package impacts QFN and flip chip technologies presented here

10. Pin placement • Generic wirebond • Dual row • Depopulated inner row • Frame, bondwires, paddle, … all couple signals • Placement is key

11. The Periphery • The periphery design (pads, ESD and IO driver cells) is integral to the design of single chip products • IOs drive signals off chip… or around the chip to sensitive circuits ESD Isolation

12. Silicon Floor plan • The IO periphery was cut into two separate domains • Local subsectors exist for further separation • Distance is #1 factor for isolation • Main aggressors are placed as far apart as possible dc2dc vco PCIe PA

13. Isolation basics • Taps typically reduce coupling by 20-30dB • Deep nwell can double that if used appropriately • Appropriately means separate and quiet ground (see next slide) tap Large tap tap epi RX TX substrate

14. Silicon Technology • Deep nwell must be tied to quiet supply and usually they are hard to come by • Must provide a very low impedance path to that ground

15. Power Delivery and isolation • First step to protecting circuits is to isolate power domains • Isolation between supplies depends on: • Regulator PSRR • Board decoupling methods

16. Power Delivery and Isolation • Generally… what works for ESD performance, increases the potential for coupling signals

17. Board coupling issue: Example Victim Aggressor Aggressor Victim Aggressor Victim

18. PMU noise coupling issue: Example • Noise from the on-chip dc-dc is well below spec for on soldered parts; but can be seen in ADC SNR (through power supply) in socketed parts • The ground connection for a the package will affect the impact of the dc-dc on circuits and the ability to couple to other parts of the product

19. DC-DC impact on receiver performance

20. Thermal issues in single-chip: Example DC-DC • Overall dissipation may remain unchanged; but the thermal density increases • This is one of the biggest limitations in integrating products • Concurrent mode operation of multi-com products becomes challenging Power Amplifier PCIe

21. Spurs in single-chip: Example • 40MHz spurs from the charge pump travel from loop filter into RX on board by proximity • Board and pin location issue, not chip or package issue

22. WiFi-BT coupling: Example Balun Balun SP3T iTR Chain A RX / TX Chain B RX only BT chain RX / TX BT WiFi 1x2 RFIC Mirror (2BT – WiFi) WiFi BT (leakedto WiFi port)

23. WiFi-BT coupling: Example continued 45o Q VDD Power Amplifier Driver I BB Pre-Driver WiFi Transmitter Chain I Q BB VSS 2*BT couples to the driver ground With default pre-driver current (18mA) With default pre-driver current (31mA) Linearize the pre-driver device by degeneration

24. Coupling through Internal Switch Balun Balun Balun Balun Balun Second Harmonic External switch SP3T iTR iTR iTR Internal switch 6-7dB better performance: Internal switch solution is differential Chain A RX / TX Chain A RX / TX Chain B RX only Chain B RX only BT chain RX / TX BT chain RX / TX BT BT WiFi 1x2 RFIC WiFi 1x2 RFIC

25. Specifications achieved for WiFi single-chip

26. Conclusions • Integration, isolation, and coexistence begins from the beginning of chip planning • One must take into account all aspects of the final product before work begins • Many low level decisions can only be answered in the context of the high level environment

27. Acknowledgements • I would like to thank the Intel Mobile Wireless Group team for all the design and testing to support this talk • I want to especially thank Jonathan Jensen, Rob Derania, Ram Sadhwani, Ryan Collins and Lei Feng for their time, testing and input.