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FE-I4a Single Chip Card issues

FE-I4a Single Chip Card issues. V. Tyzhnevyi HEP group, University of Manchester. Cut-out region (1). In order to host bulky structure consisting of PYREX+microchannels (~2.5mm) and save possibility of good bonding we are thinking of making cut-out in the SCC board;

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FE-I4a Single Chip Card issues

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  1. FE-I4a Single Chip Card issues V. Tyzhnevyi HEP group, University of Manchester

  2. Cut-out region (1) In order to host bulky structure consisting of PYREX+microchannels (~2.5mm) and save possibility of good bonding we are thinking of making cut-out in the SCC board; If we cut out AGND plane (19x45mm2) we lose AGND connection of AGND trace which hosts 8 wire bonds; There is a digital ground plane (2nd internal ground plane layer) behind AGND plate brought to C66, C67 capacitors (bottom layer) that will be broken by the cut-out; Both problems can be solved by soldering both AGND and DGND traces through wires to proper grounds. However, this problem is very crytical for AGND as it may influence performance of the readout electronics; 19mm AGND trace AGND plane 45mm

  3. Cut-out region (2) Alternative approach Leave board as it is and try to make bonding even if there is a large height difference between readout electronics and SCC board; It is necessary to make preliminary bonding trials; We can use Si sensor mock-up (Si plate covered with Ti/Pd metal layer) to emulate bonding pads of readout electronics and empty (not populated) silver finished FE-I4a SCC board; For that purpose it is necessary to order an FE-I4a SCC board. One of the possible suppliers is http://www.pcbtrain.co.uk/porviding 5 and 10 days turnaround service; Longer term option would be to change the design in such a way that it could host cut-out without breaking AGND and DGND connections;

  4. Schedule (preliminary) • Submission of the board for fabrication (either tomorrow or next Monday 8th of October) + 5 or 10 days turnaround service. So, the actual boards would arrive either by 8th or 13th October (5 days turnaround service); • We can submit FE-I4a SCC 1.0 rev even tomorrow as Gerber files are already prepared (additional holes should be added for the mechanical support of overall microcooling setup); • FE-I4a SCC 1.1 rev (current board) is not ready for submission as Gerber files should still be generated. Altium Designer (a new tool for our group) should be used for that purpose. Can take quite a while; • Before board arrives, we can design mechanical support; • After the board arrives – test bonding, test thermal properties of the microcoolingsystem+mockup of readout electronics, final assembly if the tests are successful;

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