A modified Scan Flip-flop Design to Reduce Test Power

1. Sivakumar Ganesan Sunil P Khatri Department of Electrical and Computer Engineering Texas A&M University College Station, TX A modified Scan Flip-flop Design to Reduce Test Power

2. Outline • Scan based Testing. • Impact of Test power. • Switching power • Leakage power. • Previous work on Flip-flip modification to reduce test power. • Proposed Flip-flop. • Experimental results. • Conclusion.

3. Scan based Testing Regular Flip-flop 0 1 Scanned Flip-flop Di Clk Qi FF Primary Inputs Primary Inputs Primary Outputs Primary Outputs Combinational Logic Combinational Logic Scan Data Out Di Qi-1 Scan Mode Qi 01 FF FFs FFs Clk Scan Data In • Transform flip-flops in the design into a shift register chain • In “scan” mode, we can now • Shift in test vectors • Shift out test response

4. Scan based Testing • Benefits • Transforms a sequential design into a combinational design for testing purposes • Significantly simplifies the test problem • Enables at-speed testing as well. • Drawbacks • Requires more signals to be routed in the chip, and also more pins on the package • Adds extra delay in the functional path. • Adds delay in the functional path • 2. Requires additional input signals

5. Test time Calculation • A test pattern consist of N shift cycles + 1 capture cycle (here N = number of flip-flops in a scan chain.) • If there were a total of P patterns to test the design, this would require N*P shift cycles + P capture cycles. • Test time is directly proportional to the N*P and inversely proportional to the frequency of the shift clock. • The shift frequency is limited by • Tester hardware • Power dissipation

6. Source of Power Dissipation • Dynamic Power • Historically dominated power in CMOS • Caused by signal switching • Pdyn = C V2 f • Leakage power • Non-issue a few process generations ago • Exponential increase with decreasing VT • Dominates power in recent generations • Any power reduction approach must address both

7. Power Dissipation during Scan Testing • Dynamic power • The majority of dynamic power is consumed by the flip-flop outputs (which drive the combinational logic) switching during serial shift. • Combinational logic can switch during each cycle of the scan clock. • Can be eliminated by ensuring that the combinational inputs do not switch during scan • Leakage power • Suppose combinational inputs do not change during scan • Leakage can be minimized by “parking” the combination logic in a low-leakage input state. • Typically, the leakage of a circuit can vary by a factor of 2, depending on the input state of the circuit. • Our solution addresses both types of power consumption

8. Previous Work – Latch based approach In scan mode, the “additional slave” latch is disabled, the “master” and “slave” latches form the flip-flop The Q signal going to the combinational logic does not change, thereby reducing dynamic power during scan shifting In normal mode, the “master” and the “additional slave” latches form the flip-flop. =0 =1

9. Previous Work – AND gate approach In normal mode, QEN=1, and Q, QZ follows the flip-flop output Q1. SQ, the scan data output signal, also follows Q In scan mode, QEN=0, so Q, QZ are held constant at ‘0’ and ‘1’ respectively. SQ switches as required. Hence the inputs to the combinational logic do not change, reducing dynamic power during scan shifting =0 =1

10. Proposed Scheme – Flipflop1 SE • In normal mode, SE=0 and Q as driven by the output of the DFF (Q1) • PMOS device P1 is turned off. P1 SE D Q Din Q1 • In scan mode, SE=1, so the PMOS device P1 turns on, and Q is statically 1. • Hence the combinational logic does not switch, resulting in a reduction in dynamic power during scan shifting • SQ, the scan data output, also follows the output of the DFF and drives the next flip-flop in the scan chain. SD SE SQ CLK

11. Proposed Scheme – Flipflop0 • So, by using Flipflop0 or Flipflop1, we have the same operation in normal mode • But Flipflop0 has a static 0 output in scan mode, while Flipflop1 has a static 1 output • Suppose leakage is minimized when the combinational inputs are in a particular state S. • We choose between Flipflop0 or Flipflop1 for each memory element, so that combinational inputs are in state S, in scan mode. • We thereby minimize leakage power as well as dynamic power. • In normal mode, SE=0 and Q as driven by the output of the DFF (Q1) • NMOS device N1 is turned off. SE D Q Din Q1 • In scan mode, SE=1, so the NMOS device N1 turns on, and Q is statically 0. • Hence the combinational logic does not switch, resulting in a reduction in dynamic power during scan shifting • SQ, the scan data output, also follows the output of the DFF and drives the next flip-flop in the scan chain. SD N1 SE SE SQ CLK

12. Advantages over Other Schemes • Allows us to minimize both leakage and dynamic power • Previous approaches only minimize dynamic power • Leakage power is comparable to dynamic power in recent processes. • Just require 3 more transistors per flip-flop • AND gate approach required an additional AND gate • Latch based approach required additional latch.

13. Experimental Results • We will first discuss the characterization of the new flip-flops • Flipflop1 and Flipflop0 simulated in SPICE • Report delay overhead compared to • Non-scanned flip-flop • AND gate based approach • Then we will discuss leakage improvements that can be availed using this approach • Leakage characterization of library gates • Leakage characterization for benchmark designs • Compared to AND gate based approach

14. Flipflop1 schematic

15. Flipflop1 SPICE Waveforms

16. Flipflop0 Schematic

17. Flipflop0 SPICE Waveforms

18. Delay overhead Average Delay overhead compared to normal scan flip-flop = 17.8% Average Delay overhead compared to AND gate approach = 6.6%

19. Experimental Results • Standard cells are characterized and their leakage power is calculated for all input vectors • The cells we use are NAND2, NOR2, INV, implemented in a 65nm process • We mapped several benchmarks using these cells • The leakage power consumption is calculated for these benchmark combinational designs • For the NAND gate based approach • For our approach • We assume that the inputs of the combinational logic are driven by the scan flip-flop • For our design, we choose Flipflop0 or Flipflop1 in a manner that minimizes leakage.

20. Leakage Power of Standard Cells a) Inverter b) NAND2 c) NOR2

21. Experimental Results • The leakage-minimizing vector for our approach was determined by choosing the lowest leakage vector among 10,000 randomly selected vectors. • In our approach, this vector can be applied during scan shifting, by appropriately using Flipflop0 and Flipflop1. • There are several approaches to deterministically find the vector that minimizes the leakage power of combinational circuits. • "A Probabilistic Method to Determine the Minimum Leakage Vector for Combinational Designs in the Presence of Random PVT Variations", Gulati, Jayakumar, Khatri, Walker. Integration, the VLSI Journal. • Several other competitive approaches exist as well.

22. Experimental results

23. Conclusion • We have presented an approach to reduce the total power during scan based on the use of one of 2 scan flip-flops. • Allows the designer to minimize dynamic power as well as leakage power. • Leakage power increases exponentially with newer technologies, and is comparable to dynamic power in today’s designs. • The approach reduces test power thereby • Leading to increase in the test clock frequency • Reducing test time and test cost as well. • Requires the addition of three transistors per flip-flop • Less expensive than approaches that target reduction of dynamic power (alone) • On average, leakage power reduced by ~14% using our approach • Results in a slight delay overhead of ~ 6.6% compared to earlier schemes.