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An ASIC-Style Methodology For FPGAs

An ASIC-Style Methodology For FPGAs. MAPLD Conference 2003. High-End FPGAs Face ASIC-Like Design Problems. Lengthy place and route Unpredictable place and route results Difficulty achieving and maintaining performance goals Lengthy ECOs Unnecessary design iterations Longer design time.

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An ASIC-Style Methodology For FPGAs

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  1. An ASIC-Style Methodology For FPGAs MAPLD Conference 2003

  2. High-End FPGAs FaceASIC-Like Design Problems • Lengthy place and route • Unpredictable place and route results • Difficulty achieving and maintaining performance goals • Lengthy ECOs • Unnecessary design iterations • Longer design time

  3. Root Cause:Late Problem Detection • Don’t know whether all requirements will be met until after physical implementation • Late iterations require re-implementing entire design • Instance-level fixes break each time an ECO is made VHDL or Verilog Logic synthesis Gate-level netlist Place & route No Requirements met? Yes Done

  4. What Worked In TheASIC World • Hierarchical design • Floorplanning • Integrated analysis • Congestion • Timing • Area (Utilization) • Power • Etc. VHDL or Verilog Logic synthesis Gate-level netlist ASIC-style design & analysis No Requirements met? Yes Place & route Done

  5. Why It Worked • Early, front-end analysis reduced the number of iterations • Floorplanning reduced the length of iterations • Also increased predictability of place and route results • IP reuse and teamwork methodology sped design time • Hierarchical design enabled faster ECOs

  6. Why Early Analysis • Enables rapid tradeoff (timing vs. area, etc.) iterations before place and route to meet simultaneous requirements • Reduces number of ECOs needed to attain design closure • Each ECO is isolated to a block • Iterations are faster than flat, whole-chip iterations

  7. Lessons Learned:ASIC Methodologies • 1st generation: area-based constraints • Flat routing of groups & regions • 2nd generation: block-based design • Blocks independently placed & routed • 3rd generation: integrated analysis • Timing (wireload models), congestion, utilization • 4th generation: area-based floorplanning • Hierarchical placement, flat routing and analysis • Physical and logic optimization • 5th generation: hierarchical design & floorplanning • Hierarchical floorplanning & hierarchical analysis (placement, routing, optimization)

  8. Design Example:Lengthy ECO • With a flat methodology, changes to this highlighted logic block requires a place and route iteration on the whole design

  9. Design Example:Faster ECO • With hierarchical design, logic changes are isolated to a particular block • Only need to place and route the block that changed

  10. Design Example:Congestion Problem • Early congestion analysis gives obvious visual clues anticipating potential place and route problems

  11. Design Example:Resolving Congestion • Using floorplanning, the designer has moved and merged the blocks to reduce congestion, before place and route

  12. Design Example:Timing Problem • Designer used static timing analysis to identify a critical path

  13. Design Example:Fixing Timing Problem • Designer used floorplanning to confine logic in critical path to a particular block

  14. Design Example:Timing Problems Avoided • Designer used advanced floorplanning to meet constraints by placing timing- critical I/Oregisters in physical blocks near the I/Os

  15. Design Example:Utilization Issue • Tightly packed design (98% slice and 78% RAM utilization) • Could be mapped and placed but not routed • Design was then floorplanned

  16. Design Example:Resolved Utilization Issue • Critical blocks were iteratively “crunched” to maximize utilization • Each block was individually placed & routed • Successful top-level place and route • Also met difficult timing requirements

  17. Design Example: Reused Intellectual Property (IP) • Group saved design time by reusing physical design blocks that already meet performance requirements • Used locked placement within blocks

  18. Design Example:Teamwork • Reusable IP blocks are planned first • Physical design process is started earlier, as each block becomes available from team members

  19. Methodology Example • Fully utilized 2V6000 • 99% CLB, 97% RAM • 2 priority 1 clocks notmet • P&R failed many times • 2841 timing violations • 13 hrs. 23 min. placeand route time • Alternative is to use a 2V8000 or an ASIC

  20. Step 1: Grouped Heavily-Connected Blocks

  21. Step 2: Sized Blocks Using Utilization Analysis

  22. Step 3: Compacted Blocks With Block-Based Routing

  23. Step 4: Floorplanned Compacted Blocks Together

  24. Step 5: Left Remaining Area For Routing Largest Block

  25. ASIC Methodology Results • 100% routed • ECOs in 53% less time • Clock improvement • 10% primary • 19% secondary

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