Detector & Electronics Division

1. Technology engineer with just some of the 500 FED boards. Detector & Electronics Division CMS Tracker Readout Electronics Introduction CMS is one of four gigantic particle physics experiments being built for the Large Hadron Collider at CERN. At the heart of CMS is the world’s largest silicon tracking detector which can be thought of as an enormous and tremendously fast digital camera. Technology has designed and delivered two advanced custom electronics systems which together readout and process the tremendous quantities of data generated by the silicon tracker. Embedded inside the tracker are 75,000 radiation resistant integrated circuit devices (APVs) designed to store the fast detector signals. Located outside the experiment and connected to the APVs over thousands of 70m long optical fibres are large readout boards (FEDs) which extract useful image data using sophisticated programmable digital logic arrays. • Technical Specifications • Challenge to readout data from the world’s largest silicon detector with 10 million sensor elements. • Processing 100 thousand images per second. • Total system data rate being equivalent to the contents of 2,000 CDs every second. • Analogue Pipeline Integrated Circuits (APV). Must withstand intense radiation levels. Must amplify and store analogue signals every 25 nanosecs. • FED readout board system instrumented with 15,000 Field Programmable Gate Arrays for massively parallel and flexible digital algorithm processing. APV readout chip and fitted with silicon sensor • Technical Achievements • Unprecedented system scale requiring 75,000 complex readout chips (APVs) combined with 500 large digital readout boards (FEDs). • APV pioneered the use of 0.25 deep sub-micron CMOS radiation hard process. This was subsequently adopted by all major LHC detector integrated circuits. • APV had to meet stringent low power constraints. • FED manufacture required precise reliable assembly of tens of thousands of fine pitched components, and achieved 99% good board yield. • Extremely high density logic on each FED board with 96 ADC channels @ 40 MHz, processing 25,000 strips. • Complete system delivered on time and within budget. • FED industrial partner in UK awarded CMS gold prize for industry. This work was carried out in collaboration with Imperial College London and CERN. For further information contact: John Coughlan at j.coughlan@stfc.ac.uk