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Synthesizing SRAM timing and Periphery using Synopsis

Synthesizing SRAM timing and Periphery using Synopsis. By: Jim Boley. Background and Motivation. Most SoC designs require on chip memory Design time on the order of months SRAMs consume a majority of the area and power on a digital design

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Synthesizing SRAM timing and Periphery using Synopsis

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  1. Synthesizing SRAM timing and Periphery using Synopsis By: Jim Boley

  2. Background and Motivation • Most SoC designs require on chip memory • Design time on the order of months • SRAMs consume a majority of the area and power on a digital design • To reduce this area, the bitcell array is made as dense as DRC will allow • Bitcell array consumes a majority of the total area, therefore optimizing the periphery doesn’t result in significant area savings

  3. Outline • Motivation • SRAM bitcell layout • Synthesis of periphery • Future work

  4. Outline • Motivation • SRAM bitcell layout • Synthesis of periphery • Future work

  5. SRAM Bitcell Layout BL WL BLB VDD PR PL XR Q XL QB NL NR

  6. Step 1- Place PMOS Devices PL PR

  7. Step 2- Place NMOS Pull Down devices PR PL NL NR

  8. Step 3- Place NMOS Passgate Device PR PL XL XR NL NR

  9. Step 4- Create Gate to Diffusion Contacts PR PL Q XL XR QB NL NR

  10. Step 5- Create Diffusion-M1 Contacts PR PL Q XL XR QB NL NR

  11. Step 6- Place M2 Strips BL BLB VDD PR PL XR Q XL QB NL NR

  12. Step 6- Place M3 Strips WL BL BLB VDD PR PL XR Q XL QB NL NR VSS

  13. Shared Contacts Minimize Area

  14. Shared Contacts Minimize Area

  15. Final Array- 16x16 53.84μm x 15.12μm = 814.1μm2

  16. Outline • Motivation • SRAM bitcell layout • Synthesis of periphery • Future work

  17. Decoder Synthesis module decoder( binary_in , // 4 bit binary input decoder_out , // 16-bit out enable // Enable for the decoder ); input [3:0] binary_in ; input enable ; output [15:0] decoder_out ; wire [15:0] decoder_out ; assign decoder_out = (enable) ? (1 << binary_in) : 16'b0 ; endmodule

  18. Timing/Periphery Synthesis } BL Drivers } BLB Drivers <- Decoder output

  19. Timing/Periphery Synthesis Write Read Inactive

  20. Outline • Motivation • SRAM bitcell layout • Synthesis of periphery • Future work

  21. Future Work • Bitcell array- finish power grid, add body contacts, add pins • ICC- integration of synthesized periphery with custom array (Milkyway) • Simulation of final design

  22. Questions?

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