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Statement Of Work. Define static processor, DSP Profiles, memory and bus architectures. Define interconnections between DLX and DSP processors while helping Data Path 2 group to develop switching scenarios. Determine bounds and reservation tables and work on applicable optimization issues.
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Statement Of Work • Define static processor, DSP Profiles, memory and bus architectures. • Define interconnections between DLX and DSP processors while helping Data Path 2 group to develop switching scenarios. • Determine bounds and reservation tables and work on applicable optimization issues.
SOW (Contd.) • Help define decoders for DSP Profiles. • Provide needed assistance during system testing.
November 3, 2000 • Profiles Picked. • Static Processor Picked: DLX
November 8, 2000 • Defined Hardware Profiles. • Provided DLX Hardware Details. • Provided details for DLX software tools.
November 10, 2000 • Finalized DSP Hardware Details. • Defined overall memory architecture. • Current presentation.
November 13, 2000 • Reservation Tables
November 15, 2000 • Bounds • Preliminary Design Review
December 1, 2000 • Critical Design Review
December 6, 2000 • Web-site • Final Design Review
Plan To Achieve The Goal • Create reservation tables for each DSP by 11/13 - no risks • Determine bounds on each DSP by 11/15 - Dependent on receiving FSFG from Algorithm group.
How We Fit In The Big Picture • We are designing a hardware architecture optimized to meet the algorithm group’s requirements. The other hardware groups will use the architectural framework we have provided to implement the MPEG2 decoder . We are also providing assistance to the software teams in order to create tools needed for our architecture