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David Abbott - JLAB DAQ group

Embedded-Linux Readout Controllers (Hardware Evaluation). David Abbott - JLAB DAQ group. Front-End DAQ Issues…. Front-end hardware is evolving. Real-time intelligence is moving from the CPU to FPGAs. Old hardware technologies are no longer commercially supported (FASTBUS).

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David Abbott - JLAB DAQ group

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  1. Embedded-Linux Readout Controllers (Hardware Evaluation) David Abbott - JLAB DAQ group

  2. Front-End DAQ Issues… • Front-end hardware is evolving. Real-time intelligence is moving from the CPU to FPGAs. Old hardware technologies are no longer commercially supported (FASTBUS). • CPU-Based real-time readout on a per event basis limits the maximum accepted L1 trigger rate (~10 KHz). • Computing platform and OS changes (Muli-core, more memory, 64 bit systems etc…) are not taken advantage of at the Front-End. • The v2 CODA ROC relies on older third-party technologies that are becoming impossible to upkeep on both vxWorks and Unix platforms.

  3. Current DAQ Projects • Components (v3): • CODA Objects • CODA ROC • CODA EMU (EB/ER/ANA) • Run Control • Software Tools: • cMsg • ET • EVIO • Config and Display GUIs • Hardware: • FADC/F1TDC • Trigger Interface (VME/PCI) • Trigger/Clock Distribution • Commercial Module Support • R&D: • Embedded Linux • Experiment Control • Staged/Parallel Event Building • 200KHz Trigger/readout • Clock distribution • L3 Farm

  4. Front-End Systems R&D to support fully pipelined crates capable of 200 KHz trigger rates VME CPU - (MV6100) PPC, GigE, vxWorks (GE V7865) Intel, GigE, Linux CODA ROC Readout ~160-200 MB/s Flash ADC F1 TDC TI CPU Trigger Interface - (V3) Pipeline Trigger Event Blocking Clock distribution Event ID Bank Info

  5. VXS - L1 Trigger Use VXS High speed serial backplane (P0) to collect Energy sum and hit data from FADCs Flash ADC Flash ADC VME CPU -??? Intel, GigE Linux CODA ROC VME Readout of Event Data TI CPU P0 Switch Sum and Trigger Distribution Modules (VXS) Collect Sums/Hits Pass Data to Master L1 Clock distribution Trigger Distribution

  6. GE FANUC - V7865 VME CPU • 2 GHz Intel Core Duo Processor (667 MHz Bus) • 1-3 GB DDR2 SDRAM • Dual GigE Network ports • Bootable Compact Flash port (up to 4GB) • USB 2.0 (2ports) • Optional Transition Module • 2 USB • 2 SATA • DVI-D • Optional VITA 41.3 (2 ethernet ports via P0) • VME 320 (Tempe chip - support for 2eVME and 2eSST) • Additional Hardware Extensions • 4 timers (2 microsec resolution) • Watchdog timer • 32KB User accessable NVRAM • Thermal Probes

  7. V7865 - Schematic

  8. Test Setup V7865 Running Fedora Core 6 gcc 4.1.1 2.6.18 Kernel (SMP) Boot from local SATA disk GE-Fanuc Linux SDK v2 (custom hardware support) TI VMETRO MV6100 F1TDC MV6100 Running vxWorks 5.5.1 gcc 2.96+ V7865 Trigger In Busy L1 Strobe Out

  9. General Results Interrupt Response: V7865 MV6100 Time from external signal In the TI to the IACK cycle On the VME bus : 22-23µs 6.0µs Time from IACK cycle to Execution of Callback (or ISR): 14-15µs1.5µs Total: 36-38µs7.5µs VME Write (using SDK Library) 760 ns N/A VME Write (using memory map) 350 ns 460ns VME Read (using SDK Library) 3.2 µs N/A VME Read (using memory map) 2.6 µs 1.0 µs

  10. Results - continued DMA Transfers: V7865 MV6100 Time for 400 byte transfer Over the VME Bus: BLT: 16.0 µs (25 MB/s) MBLT: 7.5 µs (53 MB/s) 2eVME: 3.7 µs (108 MB/s) 2eSST: 2.6 µs (154 MB/s) Overhead to move data to User accessible buffer: 45-75 µs 0 µs Network Performance: Max Transfer rate: 117 MB/s 79 MB/s CPU %: 12% (of 1) 100%

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