ECE 342 Electronic Circuits 2. MOS Transistors

1. ECE 342 Electronic Circuits 2. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu

2. NMOS Transistor Typically L = 0.1 to 3 mm, W = 0.2 to 100 mm, and the thickness of the oxide layer (tox) is in the range of 2 to 50 nm.

3. NMOS Transistor • NMOS Transistor • N-Channel MOSFET • Built on p-type substrate • MOS devices are smaller than BJTs • MOS devices consume less power than BJTs

4. NMOS Transistor - Layout Top View Cross Section

5. MOS Regions of Operation Resistive Triode Nonlinear Saturation Active

6. MOS Transistor Operation • As VGincreases from zero • Holes in the p substrate are repelled from the gate area leaving negative ions behind • A depletion region is created • No current flows since no carriers are available • As VGincreases • The width of the depletion region and the potential at the oxide-silicon interface also increase • When the interface potential reaches a sufficiently positive value, electrons flow in the “channel”. The transistor is turned on • As VGrises further • The charge in the depletion region remains relatively constant • The channel current continues to increase

7. MOS – Triode Region - 1 Cox: gate oxide capacitance m: electron mobility L: channel length W: channel width VT: threshold voltage

8. MOS – Triode Region FET is like a linear resistor with

9. MOS – Triode Region - 2 • Charge distribution is nonuniform across channel • Less charge induced in proximity of drain

10. MOS – Active Region Saturation occurs at pinch off when (saturation)

11. NMOS – Drain Current

12. NMOS – Circuit Symbols

13. NMOS – IV Characteristics characteristics for a device with k’n(W/L) = 1.0 mA/V2.

14. MOS Threshold Voltage The value of VGfor which the channel is “inverted” is called the threshold voltage VT (or Vt). • Characteristics of the threshold voltage • Depends on equilibrium potential • Controlled by inversion in channel • Adjusted by implantation of dopants into the channel • Can be positive or negative • Influenced by the body effect

15. nMOS Device Types • Enhancement Mode • Normally off & requires positive potential on gate • Good at passing low voltages • Cannot pass full VDD (pinch off) • Depletion Mode • Normally on (negative threshold voltage) • Channel is implanted with positive ions (VT) • Provides inverter with full output swings

16. Types of MOSFETS

17. MOS – Active Region • Saturation • Channel is pinched off • Increase in VDS has little effect on iD • Square-law behavior wrt (VGS-VT) • Acts like a current source

18. Diode-Connected Transistor When the drain and gate of a MOSFET are connected together the result is a two-terminal device known as a diode-connected transistor for saturation region. Since VGD is zero, then the device is always in the saturation region.

19. Diode-Connected Transistor incremental resistance

20. Example • An MOS process technology has Lmin= 0.4 mm, tox= 8 nm,m = 450 cm2/V.s, VT = 0.7V • Find Cox and kn’= mnCox • W/L= 8 mm/0.8mm. Calculate VGS, VDSminfor operation in saturation with ID= 100 mA • Find VGS for the device in (b) to operate as a 1 kW resistor for smallvDS

21. Example - Solution For operation in saturation region

22. Example – (con’t) Triode region with vDS very small

23. Body Effect • The body effect • VTvaries with bias between source and body • Leads to modulation of VT Potential on substrate affects threshold voltage Fermi potential of material Body bias coefficient

24. Channel-Length Modulation With depletion layer widening, the channel length is in effect reduced from L to L-DL Channel-length modulation This leads to the following I-V relationship Where l is a process technology parameter

25. Channel-Length Modulation Channel-length modulation causes iD to increase with vDS in saturation region

26. Problem A MOSFET has VT= 1 V with measured data: VGS(V) VDS(V) ID(mA) 2 1 80 2 8 91 Findl

27. Problem (cont’) Find iD at pinchoffVDSP = VGS-VT =1V

28. Problem (cont’)

29. NMOS IV Curves

30. NMOS IV Curves

31. MOSFET Circuit at DC – Problem 1 The MOSFET in the circuit shown has Vt = 1V, kn’= 100mA/V2 and l = 0. Find the required values of W/L and of R so that when vI=VDD=+5 V, rDS=50 W and vo= 50 mV.

32. MOSFET Circuit at DC – Problem 1 (cont’)

33. MOSFET Circuit at DC – Problem 2 The NMOS transistors in the circuit shown have Vt = 1V, mnCox = 120mA/V2, l = 0 and L1=L2=1mm. Find the required values of gate width for each of Q1 and Q2 and the value of R, to obtain the voltage and current values indicated.

34. Gate Capacitance • Capacitance • Depends on bias • Fringing fields are present • Account for overlap C

35. Capacitance • Gate Capacitance • CGdetermines the amount of charge to switch gate • Several distributed components • Large discontinuity as device turns on • At saturation capacitance is entirely between gate and source Define

36. MOS Capacitances • Expect capacitance between every two of the four terminals.

37. MOS Parasitics • Capacitance from gate to other 3 terminals • Diodes to body • Series resistance • Wiring parasitics

38. PMOS Transistor • All polarities are reversed from nMOS • vGS, vDSand Vtare negative • Current iDenters source and leaves through drain • Hole mobility is lower  low transconductance • nMOS favored over pMOS

39. PMOS Circuit The PMOS transistor in the circuit shown has Vt = -0.7 V, mpCox = 60mA/V2, l = 0 and L=0.8mm. Find the values required for W and R, in order to establish a drain current of 115 mA and a voltage VD of 3.5 V.