William Stallings Computer Organization and Architecture 7th Edition

1. William Stallings Computer Organization and Architecture7th Edition Chapter 4 Cache Memory Memory subsystem • Typical computer system is equipped with a hierarchy of memory subsystems, some internal to the system (directly accessible by the processor) and some external (accessible by the processor via an I/O module).

2. Characteristics • Location • Capacity • Unit of transfer • Access method • Performance • Physical type • Physical characteristics • Organisation

3. Location • CPU • Internal • External

4. Capacity • Word size • The natural unit of organisation • Number of words • or Bytes

5. Unit of Transfer • Internal • Usually governed by data bus width • External • Usually a block which is much larger than a word • Addressable unit • Smallest location which can be uniquely addressed • Word internally • Cluster on M$ disks

6. Access Methods (1) • Sequential • Start at the beginning and read through in order • Access time depends on location of data and previous location • e.g. tape • Direct • Individual blocks have unique address • Access is by jumping to vicinity plus sequential search • Access time depends on location and previous location • e.g. disk

7. Access Methods (2) • Random • Individual addresses identify locations exactly • Access time is independent of location or previous access • e.g. RAM • Associative • Data is located by a comparison with contents of a portion of the store • Access time is independent of location or previous access • e.g. cache

8. Memory Hierarchy • Registers • In CPU • Internal or Main memory • May include one or more levels of cache • “RAM” • External memory • Backing store

9. Memory Hierarchy - Diagram

10. Performance • Access time (latency) • Time between presenting the address and getting the valid data • Memory Cycle time • Time may be required for the memory to “recover” before next access • Cycle time is access + recovery • Transfer Rate • Rate at which data can be moved

11. Physical Types • Semiconductor • RAM • Magnetic • Disk & Tape • Optical • CD & DVD • Others • Bubble • Hologram

12. Physical Characteristics • Decay • Volatility • Erasable • Power consumption

13. Organisation • Physical arrangement of bits into words • Not always obvious • e.g. interleaved

14. The Bottom Line • How much? • Capacity • How fast? • Time is money • How expensive?

15. Hierarchy List • Registers • L1 Cache • L2 Cache • Main memory • Disk cache: (A portion of main memory can be used as a buffer to hold data temporarily that is to be read out to disk. Such a technique, sometimes referred to as a disk cache.) • Disk • Optical • Tape

16. So you want fast? • It is possible to build a computer which uses only static RAM (see later) • This would be very fast • This would need no cache • How can you cache cache? • This would cost a very large amount

17. Locality of Reference • During the course of the execution of a program, memory references tend to cluster • e.g. loops

18. Cache • Small amount of fast memory • Sits between normal main memory and CPU • May be located on CPU chip or module

19. Cache/Main Memory Structure

20. Cache operation – overview • CPU requests contents of memory location • Check cache for this data • If present, get from cache (fast) • If not present, read required block from main memory to cache • Then deliver from cache to CPU • Cache includes tags to identify which block of main memory is in each cache slot

21. Cache Read Operation - Flowchart

22. Elements of Cache Design • Addressing • Size • Mapping Function • Replacement Algorithm • Write Policy • Block Size • Number of Caches

23. Cache Addressing • Where does cache sit? • Between processor and virtual memory management unit • Between MMU and main memory • Logical cache (virtual cache) stores data using virtual addresses • Processor accesses cache directly, not thorough physical cache • Cache access faster, before MMU address translation • Virtual addresses use same address space for different applications • Must flush cache on each context switch • Physical cache stores data using main memory physical addresses

25. Size does matter • Cost • More cache is expensive • Speed • More cache is faster (up to a point) • Checking cache for data takes time

26. Typical Cache Organization

27. Mapping Function • Example 4.2 For all three cases, the example includes the following elements: • The cache can hold 64 KBytes. • Data are transferred between main memory and the cache in blocks of 4 bytes each. • The cache is organized as 16K = 214 lines of 4 bytes each. • The main memory consists of 16 Mbytes, with each byte directly addressable by a 24-bit address (224 =16M). • Thus, for mapping purposes, we can consider main memory to consist of 4M blocks of 4 bytes each.

28. Mapping Function • Cache of 64kByte • Cache block of 4 bytes • i.e. cache is 16k (214) lines of 4 bytes • 16MBytes main memory • 24 bit address • (224=16M)

29. Direct Mapping • Each block of main memory maps to only one cache line • i.e. if a block is in cache, it must be in one specific place • Address is in two parts • Least Significant w bits identify unique word • Most Significant s bits specify one memory block • The MSBs are split into a cache line field r and a tag of s-r (most significant)

30. Direct MappingAddress Structure • 24 bit address • 2 bit word identifier (4 byte block) • 22 bit block identifier • 8 bit tag (=22-14) • 14 bit slot or line • No two blocks in the same line have the same Tag field • Check contents of cache by finding line and checking Tag Tag s-r Line or Slot r Word w 14 2 8

31. Direct Mapping Cache Line Table

32. Direct Mapping Cache Organization

33. Direct Mapping Example

34. Direct Mapping Summary • Address length = (s + w) bits • Number of addressable units = 2s+w words or bytes • Block size = line size = 2w words or bytes • Number of blocks in main memory = 2s+ w/2w = 2s • Number of lines in cache = m = 2r • Size of tag = (s – r) bits

35. Direct Mapping pros & cons • Simple • Inexpensive • Fixed location for given block • If a program accesses 2 blocks that map to the same line repeatedly, cache misses are very highwhich is called thrashing

36. Victim Cache • One approach to lower the miss penalty Is to Remember what was discarded • Already fetched • Use again with little penalty • Victim cache is an approach to reduce the conflict misses of direct mapped caches without affecting its fast access time. • Is a Fully associative • whose size is typically 4 to 16 cache lines. • residing between direct mapped L1 cache and next memory level

37. Associative Mapping • A main memory block can load into any line of cache • Memory address is interpreted as tag and word • Tag uniquely identifies block of memory • Every line’s tag is examined for a match • Cache searching gets expensive

38. Associative Mapping from Cache to Main Memory

39. Fully Associative Cache Organization

40. Associative Mapping Example

41. Associative MappingAddress Structure • 22 bit tag stored with each 32 bit block of data • Compare tag field with tag entry in cache to check for hit • Least significant 2 bits of address identify which 16 bit word is required from 32 bit data block • e.g. • Address Tag Data Cache line • FFFFFC FFFFFC 24682468 3FFF Word 2 bit Tag 22 bit

42. Address= 0001 0110 0011 0011 1001 1100 1 6 3 3 9 C • Tag = 0000 0101 1000 1100 1110 0111 0 5 8 C E 7 • Data = FEDCBA98 • Cache line = 0001

43. Associative Mapping Summary • Address length = (s + w) bits • Number of addressable units = 2s+w words or bytes • Block size = line size = 2w words or bytes • Number of blocks in main memory = 2s+w/2w = 2s • Number of lines in cache = undetermined • Size of tag = s bits

44. Set Associative Mapping • Cache is divided into a number of sets. • Each set contains a number of lines. • A given block maps to any line in a given set. • e.g. Block B can be in any line of set i. • e.g. 2 lines per set. • 2 way associative mapping. • A given block can be in one of 2 lines in only one set.

45. Set Associative Mapping • The relationships are: m = v * k i = j modulo v where i = cache set number j = main memory block number m = number of lines in the cache v = number of sets k = number of lines in each set • This is referred to as k-way set-associative mapping.

46. mapped caches-v Associative • The next figure illustrates this mapping for the first v blocks of main memory. • For set-associative mapping, each word maps into all the cache lines in a specific set, so that main memory block B0 maps into set 0, and so on. • Thus, the set-associative cache can be physically implemented as v associative caches.

47. Set Associative MappingExample • 13 bit set number • Block number in main memory is modulo 213 • 000000, 00A000, 00B000, 00C000 … map to same set

48. mapped caches-v Associative

49. k-way Associative-mapped caches ork Direct-mapped caches • It is also possible to implement the set-associative cache as k direct mapping caches as next figure. • Each direct-mapped cache is referred to as a way, consisting of v lines. The first v lines of main memory are direct mapped into the v lines of each way; the next group of v lines of main memory are similarly mapped, and so on. • The direct-mapped implementation is typically used for small degrees of associativity (small values of k) while the associative-mapped implementation is typically used for higher degrees of associativity.

50. k-way Associative-mapped caches ork Direct-mapped caches