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BER- tester for GEB board

BER- tester for GEB board. Main components&restrictions. TLK2501 serializer / deserializer / pseudo random generator Genesys FPGA development board Multiplexer which have bandwidth more than 320 MHz 8-bit counter 16 driver chips We can test only one hybrid connector at the time

kennan-summers
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BER- tester for GEB board

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  1. BER-tester for GEB board

  2. Main components&restrictions • TLK2501 serializer/deserializer/pseudorandomgenerator • Genesys FPGA developmentboard • Multiplexerwhichhavebandwidthmorethan 320 MHz • 8-bit counter • 16 driver chips • Wecantestonlyonehybridconnector at thetime • Test line speed 320MHz

  3. TLK2501 • Can serialize and deserialize at speed of 16 x clockspeed. • Can alsogenerate PRBS(PseudoRandomBitSequency) • PRBS is 2^7-1 lenghtbitstream

  4. How to calculate BER Solution 1 Wefeedonedifferentialpair at a timewithPRBS sequence and its inversion. At theotherendof data linesXOR port is used to indicateerrorbits and feed in to thecounter. AfterPRBS sequence is sendwewillacquirecountervalueto FPGA and count BER value. Thisapproachwillneedmultiplexer to splitthatsametest to all line pairs in connector. Weprobaplyalsoneedserializer to convertparallelstreamfromcounter to serialform.

  5. How to calculate BER • Solution 2 • Wefeed PRBS sequence to every single line at a timeand returnthesignalwithcoaxialcable to the FPGA wherewecomparesendedsignalwiththesignalfromcoaxialcable. • Wewillneedmultiplexer for thisapproachalso. • There is possibiltythatsome data loss is happened in coaxialcable.

  6. Problems • Whatarerequirements for tester • How manylines at thesametimeweneed to test? • Doweneed to knowexact line whereproblem is? • How to displayresults?

  7. Suggestions/Questions

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