160 likes | 236 Views
vti_encoding:SR|utf8-nl. vti_author:SR|BREVIS\Moshe Moscu. vti_modifiedby:SR|BREVIS\Moshe Moscu. vti_timelastmodified:TR|10 Apr 2002 13:06:04 -0000. vti_timecreated:TR|10 Apr 2002 13:06:04 -0000. vti_cacheddtm:TX|10 Apr 2002 13:06:06 -0000. vti_filesize:IR|352256.
E N D
vti_cachedtitle:SR|Automated synthesis of micro-pipelines from behavioral Verilog HDL
vti_title:SR|Automated synthesis of micro-pipelines from behavioral Verilog HDL