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Electronics for D etector B uilders

Electronics for D etector B uilders. Lecture 6-7 Digital Electronics. Number systems. E xample :. a „nibble“ is a 4-digit binary number a nibble corresponds to a Hex number. Example :. and. representations of 0 to 16 in decimal , binary and Hex. Gray Code.

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Electronics for D etector B uilders

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  1. Electronics forDetectorBuilders Lecture 6-7 Digital Electronics

  2. Numbersystems Example: • a „nibble“ is a 4-digit binarynumber • a nibble correspondstoa Hex number Example: and representationsof 0 to 16 in decimal, binaryand Hex Electronics for detector builders

  3. Gray Code Gray is a binarycodewhereneighboring numbersdifferbyonlyonebit Binayandgrayhave same numberofdigitsandgn = bn The followingdigitsgidependon thetwobinarydigitsbi+1 and bi: ifbi+1 = 0  gi = bi ifbi+1 = 1  gi = bi(thusgi= 1 forbi = 0; gi= 0 for bi = 1) numbers 0 to 7 in decimal, binaryand Gray Howtogetfrombinary (bn…b3b2b1 ) toGray Code (gn…g3g2g1) ? Electronics for detector builders

  4. Boolean algebra • Boolean algebra and logical functions are key for digital logic • There are two logical states: „true” and „false” • „true“ = „1“ and „false“ = „0“ • Therearetwooperations: AND and OR • Therearecomplementaryand neutral elements • logical input states  logical output state(s) inputstates outputstates combinatoriallogic Electronics for detector builders

  5. Boolean algebra Negation: x = a (Due to Bill Gates thisnotationisused.) Note: Alternative symbolsforaarea and !a. Input Output truthtableofnegation (NOT) Electronics for detector builders

  6. AND Output Input • AND isthe0  0 operation • If a = b … = „1“, then: x = „1“ • Ifonlyoneof a, b, = „0“, then: x = „0“ • Note: • The German symbolfor a  b is a  b. • Cut it out. truthtableof AND-operation (logicalconjunction) Electronics for detector builders

  7. OR Output Input • OR isthe 1  1-operation • If a or b, or … = „1“, then x = „1“ • OR: x = a + b… • However, notethat „1“ + „1“ = „1“ • A statementcannotbetruerthantrue ! truthtableof OR-operation (logicaldisjunction) Electronics for detector builders

  8. NAND / NOR x = ab x = a+b Input Output Input Output NOR: (1  0) – operation NAND: (0  1) – operation Electronics for detector builders

  9. ExclusiveNOR / ExclusiveOR (XOR) Input Output Input Output XOR: x = a  b Exclusive-NOR: x = a  b Exclusive-NOR = Equivalenceoperation Electronics for detector builders

  10. Mathematicalpropertiesof Boolean algebra • Neutral Element • Thereis a neutral elementnforconjunctionanddisjunctionwiththefollowingproperties: • a  n = a and a + n = a • n = 1 n = 0 • ComplementaryElement • Every elementahas a complementaryelementawith: and Electronics for detector builders

  11. CommutativeLaw: and Associative Law: Note: In digital algebra: multiplication first, then addition. First AND, then OR. “PunktvorStrich” and Distributive Law: and Electronics for detector builders

  12. Absorption/RedundancyLaw: and Indentity Law: Therearenohigherpowers a2, a3 in booleanalgebra. De Morgan's Law: and or Electronics for detector builders

  13. De Morgan's Law: and or Proofof de Morgan‘slawbychecking all combinationsof a and b Electronics for detector builders

  14. Fromtruthtablestoalgebraicfunctions output variable input variables General truthtable Sumofproducts(eg. ab + ac + abe + bc) Consideronlytherows i where xi = 1. Form producttermofrow i: Includenegatedtermsaijifaij = „0“ fortheserows. Includetermsaij = „1“ unchanged. Form thesumoftheproductsof all rowsconsidering 1 and 2. Electronics for detector builders

  15. Sumofproducts: examples Example AND Example OR • Thereisonerowwith x = „1“ • a = b = „1“, • This givesproductterm „ab“ • sum all products: x = ab • considerthe last threerows • sumofproducts: • x = ab + ab + ab = ab+a (b+b) • = ab + a1 = ab + a (a+b) • = (a+a) b + a2 = b+a Electronics for detector builders

  16. A correspondingruleexiststoconstructtheProductof Sums e.g. x = (a + b) (b + c) (a + b + e) Electronics for detector builders

  17. Logicgatesymbols NOT gate OR gate AND gate NAND gate NOR gate XOR gate Electronics for detector builders

  18. Circuit with NOR, AND and OR gate Electronics for detector builders

  19. NAND and NOR as universal devices NOT: NOT gate equivalent circuit AND: • Withcombinationsof (several) NAND gatesanyothergatecanbebuiltup. • The somegoesfor NOR gates. AND gate equivalentcircuit Electronics for detector builders

  20. Logicstatescorrespondtovoltages There are many families of logic gates called CMOS, TTL, ECL … • There are input and output voltages that do not correspond to a well-defined state • The range of accepted input voltages is larger than that of output voltages Electronics fordetectorbuilders

  21. PMOS and NMOS as a switch B’ C’ NMOS A A’ PMOS B C Bild NMOS PMOS Switchingbehaviorof NMOS- and PMOS-transistors for a FET withsupplyvoltage UDD = 10 V Electronics for detector builders

  22. Inverter Inverter in CMOS-logic • Depending on voltage at E, only PMOS or only NMOS is conducting. • For E = „1”, NMOS isconductingand PMOS is not. • Thus A = „0” (b) Inverter in PMOS-logic (a) Inverter in NMOS-logic Electronics for detector builders

  23. NAND gate truthtable NAND/ 01-gate NAND in CMOS logic Electronics for detector builders

  24. NOR gate truthtable NOR / 10-gate NOR in CMOS logic Electronics for detector builders

  25. Power consumptionof CMOS logic Thereislittlecurrentflow in CMOS logic. Considerthecurrenttochargeuptheinputcapacitanceofconnectedgates The dischargevoltageof a capacitoris: Whatisthecorrespondingenergyconsumption ? Electronics fordetectorbuilders

  26. The energyneededtochargeanddischarge a capacitoris 2x Clocking CMOS logicwithfrequency f thuscorrespondsto a power consumptionof: • Power consumption in CMOS logicismiminumfor: • low pulse frequency f • lowsupplyvoltageU0or • lowloadcapacitance C • Whatdoesthisimplyforyour ASIC design andoperation? Electronics fordetectorbuilders

  27. Whatiscombinatoriallogic ? CL isthecombinationofmanyelementarylogicgatestomoregeneralandcomplexlogicalmoduls The outputstate (= result) dependsonly on thecurrentinputstates. Itdoes not depend on thehistoryoftheinputstatesorpreviousoutputstates. The numberofinputandoutputstatesneededmayvarywildly inputstates outputstates Electronics fordetectorbuilders

  28. Multiplexer • One of the inputs E is connected to A. • The value of S decides which one. Multiplexer with 3 inputs (E1, E2, E3), 1 controlline S, and 1 outputline. Multiplexer with 2 AND-gates, 1 inverter, and 1 OR-gate MUX truthtable Electronics fordetectorbuilders

  29. Multiplexer circuitwith 2 inputs (E1, E2), 1 clockgeneratorand 1 output (A) If you need to transmit the full information of all inputs (here E1 and E2), you must increase the output clock and data rate. Electronics fordetectorbuilders

  30. Decoder 2-to-4 decoderwithenableinput truthtablefor E = 1 • Think of ab as an address which asserts a single corresponding address line Ai. • E is the enable input. For E = “0”, all Ai are “0”. Circuit diagramof a 2 – to – 4 -decoder Electronics fordetectorbuilders

  31. RS-flip-flop • R is Reset, S is Set. • R = “1” (R = “0”) sets Q to “0” • S = “1” (S = “0”) sets Q to “1” • Switching from (R,S) = (1,0) to (0,0) or (R,S) = (0,1) to (0,0) does not change the output. • The state R,S = 1,1, is forbidden. It makes no sense to set and reset at the same time. Also Q and Q are not inverse. Finally the transition from (1,1,) to (0,0) is not well-defined. Electronics fordetectorbuilders

  32. Sequentiallogic • sequentiallogicdevices: • flip-flops • counter • shiftregister • forstorageofstates • called"sequentialcircuit" or "finite statemachine" (FSM) Electronics fordetectorbuilders

  33. Clocked SR flip-flop clocked SR flip-flop truthtableforclocked SR flip-flop. x = anystate Only if the clock C = “1”, can the flip-flop change state Electronics fordetectorbuilders

  34. D flip-flop clocked D flip-flop truthtableforclocked D flip-flop. x = anystate circuitsymbolofclocked D flip-flop Electronics fordetectorbuilders

  35. Triggered D flip-flops circuitsymboltriggered D flip-flop inputandoutputstatesoftriggered D flip-flopas a functionof time Electronics fordetectorbuilders

  36. Shiftregister • A shift register is a cascade of transparent flip-flops, sharing the same clock • The output of flip-flop (i) is transferred to the input of the next flip-flop (i+1) and stored Electronics fordetectorbuilders

  37. Shiftregister • Example: datasequence „1101“ • LSB first, MSB last • 4 clockcyclesareneededtotransferthebitsequenceintothe SR flip-flops 1 to 4 • The initialstateoftheshiftregisterbe „0000“ Shiftregistertruthtable Electronics fordetectorbuilders

  38. Digital pipelines at LHC • The raw data volume of the ATLAS SCT is Pb/s (≈ 6M ch. x 40 MHz x a few bits/ch.) • Zero-suppression and data compression schemes reduce this by a factor of ≈ 100 • A 132-cell pipeline buys 132 x 25 ns = 3.3 μs oflatencyforthe L1 triggerdecision • Note thesecondpipeline, thederandomizingbuffer(3x8 eventsdeep) Electronics fordetectorbuilders

  39. Pattern recognitionwith a SR This circuitrecognizesthebitsequence„1101“ in an arbitrarystringofdata Note thatthisrequirestoaccesseach FF in parallel Electronics fordetectorbuilders

  40. Trigger basics (ATLAS) Lot’s of data!! Raw data before L1 trigger: ~10 Pbyte/sec LEVEL 1 Input rate: ~ 1 GHz (40 MHz x 25 events) Accept rate: 75 KHz  130 Gbyte/sec Processing time: ~2 µsec; Latency: 2.5 µsec Technologies: Electronics/Firmware LEVEL 2 Accept rate: 2 KHz  1.3 Gbyte/sec Processing Time: ~40 ms  Region of Interests Technologies: Firmware, Software/Networks Event Filter Accept Rate: 200 Hz  up to 400 Mbyte/sec Processing Time: ~4 sec Technologies: Software/Networks L1 L2 L3

  41. State diagram of a 2-bit SR • We have 4 states (Z1 – Z3) corresponding to the content of the SR • Depending on the value of the new bit (nb) to move into the SR, the state Z is changed or not. • We introduce the variables A1A0 to indicate the old content of the SR, N1N0 to indicate the new content, and the output variables Q1Q0 (with Q1Q0 = A1A0) . Electronics fordetectorbuilders

  42. From state diagram, to state table, to state equation nb 1 0 Electronics fordetectorbuilders

  43. Patter recognition of “101” with a SR • We have 4 states (Z1 – Z3) depending on the number of matching bits in the SR • The output variable Q0 indicates if a pattern matches (Q0 = “1”) not (Q0 = “0”). Electronics fordetectorbuilders

  44. From state diagram, to state table, to state equation N1 No

  45. Transmission gate CMOS transmissiongate: theinverterofthecontrolinputis not shown truthtableoftransmissiongate: Z = high impedanceoutput Electronics for detector builders

  46. Data Memory • Memory canbeasormoreimportantthanprocessing power ordatatransmissionbandwidth • Whatmemorycharacteristicsshouldyoucarefor ? • Volatile or non-volatile („permanent“ storage) • Memory sizeanddensity • Write andreadtimes • In someapplications, watchradiationhardness • (volatile: dataisonlystoredduring power on) Electronics for detector builders

  47. Memory types • ROM (Read-onlymemory) • RAM (Random accessmemory) • Flash memory • magneticmemory (tape, standardharddrive) • opticalmemory (CD, DVD) Electronics for detector builders

  48. DRAM A DRAM (Dynamic RAM) cellconsistsof a capactor, transsitorswitchand dataandaddresslines • informationisstoredascharge on a capacitor • charge must berefreshedeveryfewms due toleakage • DRAMs arecompactandinexpensive • Same principleisused in analog pipelinesofmanydetectorreadout ICs Electronics for detector builders

  49. SRAM A SRAM (staticRAM) cellconsistsofcross-coupledinverters (flip-flops) • SRAMs are fast and do not needrefreshing • Power consumptionislessthan in DRAMs • SRAMs arelesscompactthan DRAMs andaremore expensive • SRAM principleisused in digital pipelinesofsomedetectorreadout ICs Electronics for detector builders

  50. SRAM DDR SDRAM = Double Data Rate Synchronous DRAM Photoof a DDR SDRAM from Infineon for PC memory Electronics for detector builders

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