1 / 38

Timing-aware Energy/Correctness Optimization for Probabilistic BooleaN Circuits

Timing-aware Energy/Correctness Optimization for Probabilistic BooleaN Circuits. Ching -Yi Huang & Yung-Chun Hu & Black 2013/10/14. Outline. Introduction Previous works Issues & motivation Problem formulation & key ideas Proposed algorithm Initial Replacing Cell selection

kenton
Download Presentation

Timing-aware Energy/Correctness Optimization for Probabilistic BooleaN Circuits

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Timing-aware Energy/Correctness Optimization forProbabilistic BooleaN Circuits Ching-Yi Huang & Yung-Chun Hu & Black 2013/10/14

  2. Outline • Introduction • Previous works • Issues & motivation • Problem formulation & key ideas • Proposed algorithm • Initial Replacing • Cell selection • Further Optimization • Future work

  3. Introduction (1/3) Noise effect Lower VDD

  4. Introduction (2/3) Energy per switching: Energy ratio p

  5. Introduction (3/3) • Probabilistic operations • OR: ∨p • AND: ∧p • NOT: ¬p • Let probabilistic parameter p= 0.9 A 0.9 F B

  6. Previous works Exact method MC method Formula-based method

  7. Previous works • Strategies of correctness optimization Random assignment Observability-based assignment

  8. However… • 1. Let us locate the position of MC method • Used for quick evaluation or verification? • How about hybrid with formula-based method? • 2. The observability-based correctness optimization • Did not consider the energy consumption/reduction • Did not propose how to choose the probabilityp for p-gate • Did not consider the circuit delay

  9. Issues • Supply voltage vs. probability (on 45nm) • Other influences of voltage-scaling • Cell characterization • Multiple supply voltages

  10. V-P & E-P • PTM 45nm bulk • Vtn 0.466 ; Vtp 0.412 • Wn 0.415 ; Wp 0.63; L 0.5 • Standard deviation 0.24 0.22 0.20 0.18 • Cell function: INV, NAND

  11. V-P p p 11 Vdd (V) Sd=0.24, max_p = 0.9857 Sd=0.22, max_p = 0.9911 Vdd (V) p p Vdd (V) Vdd (V) Sd=0.20, max_p = 0.9951 Sd=0.18, max_p = 0.9977

  12. P-E Energy (normalized) Energy (normalized) 1.1 V 0.8 V 0.5V p Sd=0.24, max_p = 0.9857 p Sd=0.22, max_p = 0.9911 Energy (normalized) Energy (normalized) Sd=0.20, max_p = 0.9951 Sd=0.18, max_p = 0.9977 p p

  13. Other influence of voltage-scaling • Supply voltage • Delay • Driving strength • Leakage power (static power) • Switching power (dynamic power) • The “energy” we care = power × delay P = VDDIDDQ+COUTVDD2 f ?

  14. Cell characterization • Why cell characterization is necessary • timing-aware • power-aware • Arcs • CCS, ECSM, NLDM • Synopsys – Liberty NCX

  15. Multiple supply voltages • How many? • Should be as reasonable as possible • What values? • > both Vth of pmos and nmos

  16. Outline • Introduction • Previous works • Issues & motivation • Problem formulation & key ideas • Proposed algorithm • Initial Replacing • Cell selection • Further Optimization • Future work

  17. Problem formulation Objective 1 • Given • A deterministic circuit (every p=1) • Correctness constraint (rate/magnitude) • Derive • Energy optimized PBC • Considering circuit delay (little suffer) Objective 2 • Given • A deterministic circuit (every p=1) • Energy constraint (% of reduction) • Derive • Correctness optimized PBC • Considering circuit delay (little suffer) Timing-aware !!!!!

  18. Key ideas • Timing • Keep intact (no timing violation or little suffer) • Probability selection • Scalable enough algorithm to deal with different # of p • P-gate selection -> cell selection • Energy optimization • Correctness optimization

  19. Energy optimization 22 • As many P-gates as possible • Lower observability first • Avoid placing at critical paths • Correctness is not proportional to the # of P-gates constraint

  20. Correctness optimization 23 • Lower observability first • Avoid placing at critical paths • The energy reduction should be proportional to the # of P-gates constraint Normalized energy consumption Ratio of probabilistic gates (%)

  21. Trade-off between p and E • p • Correctness -> # of P-gates • Energy -> total energy ? -> Need observation • Initial replacing • Based on the observation, determine where to change p • Iterative cell selection algorithm • Similar to gate sizing

  22. Evaluation • In algorithm • Correctness • Formula-based method • Delay & Power • Simple calculation • Estimation based on the information of cells • Not considering false paths • Final check • PrimeTime/PrimePower • Proposed MC method

  23. Comparison • 1. Random assignment • 2. Previous work (observability-based assignment) • 3. Design Compiler

  24. Outline • Introduction • Previous works • Issues & motivation • Problem formulation & key ideas • Proposed algorithm • Initial Replacing • Cell selection • Further Optimization • Future work

  25. Proposed algorithm • Replace lower observability first • Avoid placing at critical paths • Select voltage (probability) • correctness sensitivity estimation • Estimate correctness/energy after every placing • Final check with a little tuning Initial replacing Cell selection Further optimization

  26. Proposed algorithm Initial replacing Cell selection Selection algorithm Further optimization

  27. Proposed algorithm Initial replacing Cell selection • Approximate PBC minimization • Calculate observability • Find near 0 or 1 signals • Evaluate correctness • Remove near-redundant wire according to observability and the diff of correctness • Final check Further optimization

  28. Redundant Removal • In deterministic circuit, we can inject SA faults and remove redundant wires. SA fault Observable? No Remove the wire

  29. Near-redundant removal • In PBC, we may regard signals which have high probability to be 0 or 1 as stuck-at-faults. E A 0.0375 w 0.9 0.9625 0.3 B 0.075 Correctness=0.99375 0.25 C D If every PI has probability of 0.5 to be 1, w has probability of 0.9625 to be 0.

  30. Near-redundant removal • In PBC, we may regard signals which have high probability to be 0 or 1 as stuck-at-faults. 0 Correctness=0.977 The node reduction is 66%.

  31. Approximate PBC minimization Start Identify near-redundant wires Select the node with lowest observability Recalculate observabilty & Re-simulate circuit Check the correctness suffering Yes Remove the near redundant wire Pass ? No Yes Other candidates No Final check & restore Report energy consumption Report correctness Derive final PBC Finish

  32. Correctness definition with respect to applications • Correctness rate vs. correctness magnitude • Others’ definition • Relative error = POorig / POapprox×100% • Error magnitude = (|POorig-POapprox|)/|POmax| ×100% • Error rate (ER) : the percentage of vectors for which the values at a set of outputs deviate from the error free responses, during normal operation. • Error significance (ES) for a set of outputs : defined as the maximum amount by which the numerical value at the outputs of an imperfect circuit version can deviate from the corresponding value for the perfect version • RS = ER*ES

  33. Application (1/2)

  34. Application (2/2) Assume each PO has same weight, the average correctness is 0.9.

  35. Future work • Learn Liberty NCX • Cell characterization and observation • Correctness redefinition • What technology? (45nm, 90nm, 130nm, 250nm) • More applications (benchmarks referenced by papers) • Merge near-identical signals?

More Related