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Table A.1. The VHDL operators.

Table A.1. The VHDL operators. Figure A.1. The general structure of a VHDL design entity. Figure A.3. The general form of an architecture. Figure A.4. Code for a full-adder. Figure A.5. The general form of a PACKAGE declaration.

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Table A.1. The VHDL operators.

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  1. Table A.1. The VHDL operators.

  2. Figure A.1. The general structure of a VHDL design entity.

  3. Figure A.3. The general form of an architecture.

  4. Figure A.4. Code for a full-adder.

  5. Figure A.5. The general form of a PACKAGE declaration.

  6. Figure A.6. The general form of a component declaration.

  7. Figure A.7. Code for a four-bit adder, using component instantiation.

  8. Figure A.8. Instantiating a four-bit adder from the LPM library.

  9. Figure A.10. Using a compoonent defined in a package.

  10. Figure A.11. Code for a four-bit adder, using arithmetic expressions.

  11. Figure A.12. A priority encoder described with a conditional signal assignment.

  12. Figure A.15. A n-bit adder.

  13. Figure A.20. A PROCESS statement.

  14. Figure A.23. A FOR-LOOP that does not represent a sensible circuit.

  15. Figure A.24. The FOR-LOOP from Figure A.23 using a variable.

  16. Figure A.25. The circuit generated from the code in Figure A.24.

  17. Figure A.26. Using a variable to describe an n-input NAND gate.

  18. Figure A.27. The code from Figure A.26 using a signal.

  19. Figure A.29. A gated D Latch.

  20. Figure A.30. D flip-flop.

  21. Figure A.31. Equivalent code to Figure A.30, using a WAIT UNTIL statement.

  22. Figure A.32. D flip-flop with asynchronous reset.

  23. Figure A.33. D flip-flop with synthronous reset, using an IF statement.

  24. Figure A.34. D flip-flop with synchronous reset, using a WAIT UNTIL statement.

  25. Figure A.35. Code for a four-bit register with asynchronous clear.

  26. Figure A.36. Code for an n-bit register with asynchronous clear. Figure A.36. Code for an n-bit register with asynchronous clear.

  27. Figure A.37. VHDL code for an n-bit register with an enable input.

  28. Figure A.38. Code for a four-bit shift register.

  29. Figure A.39. The code from Figure A.38, using a variable.

  30. Figure A.40. An example of a counter.

  31. Figure A.41. The accumulator circuit.

  32. Please see “portrait orientation” PowerPoint file for Chapter 10 Figure A.42. Component declarations for the accumulator circuit.

  33. Please see “portrait orientation” PowerPoint file for Chapter 10 Figure A.43. Code for the accumulator circuit.

  34. Figure A.44. State diagram of a simple Moore-type FSM.

  35. Please see “portrait orientation” PowerPoint file for Chapter 10 Figure A.45. An example of a Moore-type finite state machine.

  36. Please see “portrait orientation” PowerPoint file for Chapter 10 Figure A.46. Code equivalent to Figure A.45, using two processes.

  37. Figure A.47. State diagram of a Mealy-type FSM.

  38. Please see “portrait orientation” PowerPoint file for Chapter 10 Figure A.48. An example of a Mealy-type Machine

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