1 / 35

Electrocardiogram (ECG) application operation – Part A

Electrocardiogram (ECG) application operation – Part A. Final Presentation. Performed By: Ran Geler Mor Levy Instructor: Moshe Porian Project Duration: 2 Semesters Spring 2012. Contents. Introduction Top Architecture Overview Data Flow Components Simulations Performance

kerem
Download Presentation

Electrocardiogram (ECG) application operation – Part A

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Electrocardiogram (ECG) application operation – Part A FinalPresentation Performed By: Ran Geler Mor Levy Instructor: Moshe Porian Project Duration: 2 Semesters Spring 2012

  2. Contents • Introduction • Top Architecture • Overview • Data Flow • Components • Simulations • Performance • Problems in developing process • Conclusions • Part B schedule

  3. Introduction • The heart is a muscular organ that beats in rhythm to pump blood through the body • By analyzing the heart behavior and especially the electrical impulses we can help identify heart diseases and special circumstance that require close monitoring

  4. Medical Terms • ECG • Lead • Bipolar leads • Unipolar leads • Precordial Leads

  5. Project Overview

  6. Project Goals • Portable ECG device based on FPGA • Integrating Multi Platforms elements • ECG DB with FPGA • Interactive GUI with debugger abilities (Part B) • Methodic project

  7. Top Architecture

  8. What we have achieved: • Implementing ECG controller • ECG FSM • Integration with peripheral components. • Examination of the Implemented components • Creating tests bench • Mocking TI DB behavior • P& R to projects top architecture by Quartus • Adding Flash memory support

  9. Top Architecture – Data Flow

  10. Top Architecture – Frequency Frequency requirements for modules MATLAB GUI: Rx / Tx Via UART interface @ frequency of 115,200Hz FPGA: Main frequency: 100MHz Rx / Tx Modules @ frequency of 115,200Hz ADS1928R: Main frequency: 2.048MHz SPI-Data Out freq’: >110KHz Flash Memory: Main frequency: 100MHz

  11. Core microarchitecture Data Rate: 100MHz 512Bytes Data Rate: >110KHz

  12. Core Architecture • ECG FSM • FIFO • Command & Aux Regs • Wishbone Master & Slave • SPI Core

  13. ECG FSM • Controls the flow of data between the host and the DB • Three Main chain of actions: • Read Data • Read Registers • Write Registers

  14. ECG FSM - Graph

  15. FIFO at ECG Controller • FIFO Size: 512 Bytes. • Stores Instruction and Sampled data. • Data structure on Instruction case: 1st Command 2nd Command Operation Commands (ex: RDATAC, Rreg, Wreg, Standby, Reset, ect’..) Additional Data Optional: Second Byte for (Rreg, Wreg) and sample interval for RDATAC command. Data for commands

  16. SPI • The SPI Interface frequency: • At 24bit resolution per 8 Electrodes and 500 Samples per Sec: • Active at low. i.e. CS = ‘0’

  17. Flash Component WBS Flash Component FLASH Flash FSM Flash Controller RAM 256Byte Reset en

  18. Flash Component - Flash • One sample(24bit res. per 8 Electrodes)= 27Byte. • Lets assume sample rate of 500 SPS • Flash size = 4MB • Therefore we can sample for 5min.

  19. Flash Component – Flash client BUS Technical Demands: • Common FLASH Interface protocol (CFI) • Wishbone Interface • Performs Read, Write, Reset and Erase transactions • Initiative read on power-on • Contains a timeout algorithm • Generic: adaptable to different FLASH sizes and clock frequencies. CFI Wishbone

  20. ADS1298R ECG DB • Texas Instruments Card • Arrived to the High Speed Digital Systems Lab

  21. Test Methodologies • Operation of the ECG Controller: • Checking that states change are at time • Checking control signals & data signals between units • Non existing commands • NOTE: When a transaction is executed the wishbone “stall” signal is raised to ‘High’, So other requests will remain pending at the Rx Wishbone Master.

  22. ECG Controller TB Data Flow • We have implemented a special closed component for Testing.

  23. DB mocking • We have implemented a component that is imitating the TI DB behavior.

  24. ADS1298R ECG DB

  25. Simulations – Read Transaction example • Top Architecture Wave. Flash Rx Transaction SPI

  26. Simulations – Read Transaction example • SPI Transaction

  27. Simulations – Read Transaction example • Flash transaction

  28. Simulations – Read Transaction example • FIFO Usage

  29. Quartus Simulations • General Layout

  30. Quartus Simulations • Max Frequency

  31. Quartus Simulations • Top Arc Synthesis summary

  32. Problems in developing process • Meet timings requirements of the TI Evaluation board. • Keep the projects specifications and requirements while adding more logic to the top arch. • Debug and testing of the whole implemented logic.

  33. Conclusions • We learned a lot about the developing process & the importance of good planning a head • The importance of working organized • How much good documentation of previous project is important

  34. Schedule – Part B 1w 1w 3w 1w

  35. Schedule – Part B Cont. 1w 1w

More Related