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DC/DC Converter with Transparent Electronics for application on Photovoltaic Panels

Master of Electrical and Computers Engineering. DC/DC Converter with Transparent Electronics for application on Photovoltaic Panels. Romano Torres 19th July 2013. Supervisor: Vitor Grade Tavares Second Supervisor: Pedro Miguel Cândido Barquinha

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DC/DC Converter with Transparent Electronics for application on Photovoltaic Panels

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  1. Master ofElectricalandComputersEngineering DC/DC Converter withTransparentElectronics for applicationonPhotovoltaicPanels Romano Torres 19th July 2013 Supervisor: Vitor Grade Tavares Second Supervisor: Pedro Miguel Cândido Barquinha Second Supervisor: Pydi Ganga Bahubalindruni

  2. Outline • Motivation • Objectives • a-IGZO TFTs • DC/DC Converter • Amplifier • Regulator • Fabrication • Conclusions • Future Work

  3. Motivation • To constructcircuitsonflexiblesubstracts, such as plastic, glass: • Possible to embody in photovoltaicpanels. • Lowcostfabricationatroomtemperature.

  4. Objectives • Design of a boost DC/DC converter usingtransparentelectronics in order to haveanincreasedandstablevoltagelevelwithdirectcurrent. • Vout > 1.5*Vin; • Efficiency >= 40% • Fabricationofthecircuit in CENIMAT/UNL.

  5. a-IGZO TFTs Problems: • High parasitic resistance; • P-type transistors with low performance; • Threshold voltage shift. Staggeredbottom-gate TFT structure

  6. VoltageBoostingStage – DC/DC converter • Indutors are avoided due to their low performance in transparent technology; • Capacitor is used to save charge in electric field; • Vdd < Vout < 2*Vdd

  7. VoltageBoostingStage - out ofphaseclocksignals Lower variation of Vout level.

  8. 2 Voltage Boosting Stages in Cascade • To increasethevoltageleveltwice; • Parasiticeffectsreducetheefficiency; • 4 TFTsof 320 μm in parallel for eachdiode-connection are used; • Vdd < Vout << 3*Vdd

  9. SeparationbetweenBoostingStages • Allow a stable voltage level at node E; • Avoid clock feedthrough in TFT1 and TFT2.

  10. 3 BoostingStages in Cascade • Proposed DC/DC converter includes 3 VoltageBoostingStages; • Settling time isincreased.

  11. Bootstrapping Stage – Proposed DC/DC converter • Bootstrappingstageisused to reducethesettling time ofthecircuit; • Powerconsumptionisnegligble; • Smallcapacitorsandtransistors can beused.

  12. Comparisonwithprevious DC/DC converters in thesametechnology DC/DC converter fromotherauthors Proposed DC/DC converter

  13. DC/DC Converter - Simulation Output voltage Bootstrapping Cross-connected WithLoad I_load = 162 μA Vout=16.37 V WithoutLoad Vout=35.5 V

  14. Efficiency • Thesuppliedcurrentofeachvoltagesourceismeasured (I_in=167 μA); • Thecurrentsmultipliedbythesuppliedvoltage (Vin=10V) are added, resulting in the input power; • Withthesamecurrent for eachvoltagesource, efficiencyis: • Thecurrentsupplied in bootstrappingstageisverylow (I_bs=0.12μA); • Theefficiencyis: 39.93%

  15. 3 VoltageBoostingStages - Simulation Voltagelevels for eachstage

  16. DC/DC converter - Layout 3068.55 μm 5793.55 μm

  17. 10 DC/DC converters in parallel - Theequivalentresistanceof 10 converters in parallelislowerthanwithonlyone converter. Output voltage

  18. Final circuitwithregulation • Circuitspecifications: • Vdd = 10 V • R1 andR2 >> RL • Objectives: • Vout≃ 20 V • 50% lowerΔV • Advantage: • More stablevoltagelevel • evenwithloadvariation.

  19. ProposedAmplifier – Blockdiagram

  20. Amplifier

  21. DifferentialStage

  22. Positive Feedback Stage

  23. Source-FollowerStages

  24. Common-SourceStages

  25. PhaseCompensation -In order to havehigherphasemargin.

  26. GainandPhase Response • Gain: 36.7dB • Phase Margin: 83.79°

  27. ProposedAmplifier - Layout 2383.8 μm 2450 μm

  28. Regulator Voltagelevels Vout = 17.65 V Thevoltagevariationwiththeloaddecreased 80%.

  29. Final Circuit - Layout 14557.1 μm 18709.55 μm

  30. Fabrication DC/DC converter with bootstrapping and 2 boosting stages

  31. Conclusions • DC/DC converter: • Wide transistors reduce parasitic resistance; • Bootstrapping stage decreases settling time; • 10 converters in parallel reduce the parasitic resistance and allow more voltage boosting stages, increasing the output voltage level. • Amplifier: • Good phase margin was achieved; • Voltage gain is enough for the regulation; • Regulator: • 80% lower fluctuation of the voltage level with load variations.

  32. Future Work • Improve the design oftheamplifier to increasethegain; • PWM regulationwithduty-cyclevariation.

  33. TheEnd Thankyou!

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