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Chapter 4: Computer Organization

Chapter 4: Computer Organization. Prof. Steven A. Demurjian, Sr. † Computer Science & Engineering Department The University of Connecticut 191 Auditorium Road, Box U-155 Storrs, CT 06269-3155. steve@engr.uconn.edu http://www.engr.uconn.edu/~steve (860) 486 - 4818.

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Chapter 4: Computer Organization

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  1. Chapter 4: Computer Organization Prof. Steven A. Demurjian, Sr. † Computer Science & Engineering Department The University of Connecticut 191 Auditorium Road, Box U-155 Storrs, CT 06269-3155 steve@engr.uconn.edu http://www.engr.uconn.edu/~steve (860) 486 - 4818 † These slides have been modified from a set of originals by Dr. Gary Nutt.

  2. Purpose of this Chapter • Review Material on Computer Architecture • Today’s Process has Foundation in Sequential Execution of Program on Set of Data • Execution on von Neumann Architecture • Hardware Components have Direct and Indirect Interaction with Operating System Components • Critical Underlying Concepts for OS • Remember, OS Bridges Hardware and Software • OS Must Interact with Hardware or Hardware Abstraction Layer in Kernel • OS Must Provide Services to Software Systems and Applications

  3. von Neumann Architecture • Combination of … • CPU (ALU + Control Unit) • Primary or Executable Memory • I/O Devices & their Controllers • Execution Process Involves • Program & Data Copied into Primary Memory from External Source • Control Unit Reads, Decodes, Executes Instructions • ALU Arithmetic and Logical Operations • Data and Address Buses Facilitate Interaction Between Components

  4. von Neumann Architecture Arithmetic-Logical Unit (ALU) Control Unit Data Bus Address Bus Primary Memory (Executable Memory) Device Device Device

  5. The Arithmetic Logic Unit (ALU) • Composed of … • Functional Unit to Perform Arithmetic and Logical Operations • Set of General and Status Registers • General Registers Utilized for Operands and Result of Operations • Status Registers Used by CPU to Store In-Progress Calculations • Three Step Computation Process • Load Values into General Registers • Perform Arithmetic on Registers • Save Results Back to Primary Memory

  6. ALU Right Operand Left Operand R1 R2 . . . Rn Functional Unit Status Registers Result To/from Primary Memory

  7. Language Translation: Source to Assembly to Machine Source int a, b, c, d; . . . a = b + c; d = a - 100; Assembly Language ; Code for a = b + c load R3,b load R4,c add R3,R4 store R3,a ; Code for d = a - 100 load R4,=100 subtract R3,R4 store R3,d Machine Language 10111001001100…1 10111001010000…0 10100111001100…0 10111010001100…1 10111001010000…0 10100110001100…0 10111001101100…1

  8. The Control Unit • Executes Sequence of Instructions Stored in Memory • Three Step Process • Fetch Instruction from Primary Memory • Decode the Instruction • Execute the Instruction • Program Counter (PC) Maintains Memory Address of Currently Executing Instruction • Instruction Register (IR) Copy of Fetched Instruction

  9. Control Unit load R3,b load R4,c add R3,R4 store R3,a 10111001001100…1 10111001010000…0 10100111001100…0 10111010001100…1 3046 3050 3054 3058 Primary Memory Control Unit Fetch Unit 3050 PC Decode Unit IR load R4,c Execute Unit

  10. Control Unit Operation • Fetch phase: Instruction Retrieved from Memory • Execute phase: ALU Operation, Memory Data Reference, I/O, etc. • Fetch & Execute Phases Overlapped • Fetch Next While Executing Current • Nearly Two-Fold Performance Improvement PC = <machine start address>; IR = memory[PC]; /* FETCH */ haltFlag = CLEAR; while(haltFlag not SET) { execute(IR); PC = PC + sizeof(INSTRUCT); IR = memory[PC]; /* FETCH */ };

  11. Bootstrapping • Process for Starting or Restarting Hardware • Utilizes Fetch-Execute Algorithm • First Instruction Hardwired and Fetched from Read-Only Memory (ROM) • Facilitated via Read-Only Memory (ROM) • Control Unit Starts and Branches to Fixed Memory Location (PC Points to ROM) • Bootstrap Loader Begins Loading OS • Once Loaded, PC Points to OS and Begins Executing OS • Hence, Brings Up OS

  12. Bootstrapping 2 3 Loader OS Bootstrap loader (“boot sector”) 1 Primary Memory 4. Initialize hardware 5. Create user environment 6. …

  13. Memory • Primary Memory Stores Both Programs and Data • Utilization of Three Registers • Memory Address Register (MAR) • Memory Data Register (MDR) • Command Register (CMD) • To Write to Memory • Data Placed in MDR • Address Placed in MAR • write Command Placed in CMD • To Read from Memory • Address Placed in MAR • read Command Placed in CMD

  14. Memory Unit 0 MAR 1234 1 2 MDR 98765 Command write 1234 98765 n-1

  15. Devices & Device Controllers • Wide Variety of Devices and Formats • Storage (Magnetic Tape/Disk) • Multi-Media (Display, CD or DVD) • Character (Terminal or Keyboard) • Communication (Serial Port/Network Interface) • Which are Block-Oriented? Char-Oriented? • Device Controller • Hardware Connected to Address/Data Bus • Provides Hardware Level Interaction Between Device and Other Hardware Components • Commonality Among Controllers via Abstract Operations • Every “Printer” has Same Abstract Interface

  16. Device Organization Application Program Abstract I/O Machine Device Controller Device • Device Manager/Device Driver • Program to Manage Device Controller • Supervisor Mode Software

  17. Device Controllers • Responsible for Constantly Monitoring Device • Status, Commands, Error Correction • Custom Hardware - Device Controller • Device Controller Interface (DCI) • Provides Means to Allow Devices of a Vendor to Connect to Devices of Another Vendor • SCSI (Small Computer Serial Interface) • DCI is Software that contains … • Flags (Busy/Done) • Status Register Interface (to Set/Check Flags) • I/O Command Buffer • Data Buffers - Stage Data Between Device and Hardware Component (Memory, CPU, etc.)

  18. Device Controller Interface busy done 0 0 idle 0 1 finished 1 0 working 1 1 (undefined) . . . busy done Error code . . . Command Status Data 0 Data 1 Logic Data n-1

  19. Device Drivers • Software Interface Between OS and Device Controller Interface • Examined in Detail in Chapter 5 Printer Driver Terminal Driver Disk Driver Terminal Controller Printer Controller Disk Controller

  20. Performing a Write Operation • CPU Waits While Device Operates • Devices Much Slower Than CPU • Would Like to Multiplex CPU to a Different Process While I/O Is Taking Place • Support for Asynchronous I/O • CPU Starts I/O • CPU Switches to Another Active Program • Interrupt When I/O Completes while(deviceNo.busy || deviceNo.done) <waiting>; deviceNo.data[0] = <value to write> deviceNo.command = WRITE; while(deviceNo.busy) <waiting>; deviceNo.done = TRUE;

  21. Example: Asynchronous Database I/OMessage Passing, Queuing & Interrupts DB Request Manager • Users Submit SQL Requests • DB Manager Queues Requests • Process First Request in Queue • Send I/O Request to DB I/O Process • Process Next Request in Queue, etc… • DB I/O Process Queues I/O Requests • Sends First Read/Write to Driver • Sends Second Read/Write to Driver • Interrupt from Driver for First R/W • Send Result to DB Request Manager • DB Manager Continues to Process Queued Reqs • Element is DB I/O Process Result • Interpret Result and Send Response to User DB I/O Process I/O Interrupt Disk Driver I/O Interrupt Disk Controller

  22. Control Unit with Interrupt • Interrupt - Signal from Hardware to Software • Notification from Device that I/O Completed PC = <machine start address>; IR = memory[PC]; haltFlag = CLEAR; while(haltFlag not SET) { execute(IR); PC = PC + sizeof(INSTRUCT); IR = memory[PC]; if(InterruptRequest) { memory[0] = PC; PC = memory[1]; } };

  23. Interrupt Handler • Part of OS Executed When Device Finishes I/O • Context Switch Saves State of Current Process in order to Respond to Interrupt • What if Second Interrupt Occurs Before First has Finished Processing? interruptHandler() { saveProcessorState(); for(i=0; i<NumberOfDevices; i++) if(device[i].done) goto deviceHandler(i); /* something wrong if we get to here … */ deviceHandler(int i) { finishOperation(); returnToProcess(); }

  24. A Race Condition saveProcessorState() { for(i=0; i<NumberOfRegisters; i++) memory[K+i] = R[i]; for(i=0; i<NumberOfStatusRegisters; i++) memory[K+ NumberOfRegisters+i] = StatusRegister[i]; } PC = <machine start address>; IR = memory[PC]; haltFlag = CLEAR; while(haltFlag not SET) { execute(IR); PC = PC + sizeof(INSTRUCT); IR = memory[PC]; if(InterruptRequest && InterruptEnabled) { disableInterupts(); memory[0] = PC; PC = memory[1]; } };

  25. Ensuring that trap is Safe • Trap Instruction Dispatches Routine Atomically • A Trap Handler Performs Desired Processing • “A Trap is a Software Interrupt” • In Following, PC Set to 1st Instruction for Relevant Trap Handler executeTrap(argument) { setMode(supervisor); switch(argument) { case 1: PC = memory[1001]; // Trap handler 1 case 2: PC = memory[1002]; // Trap handler 2 . . . case n: PC = memory[1000+n];// Trap handler n };

  26. Concluding Remarks/Looking Ahead • Review of Computer Organization • Core Concepts and Terms • Relationship of Hardware to OS Components • Interplay of Hardware and Software Concepts (Interrupt and Trap) • Interesting Exercise 8 in Section 4.8 • Utilize C++ and Inheritance for OO Design • Design of Functions/Private Data for Keyboard, Display, Mouse, Serial Line Printer, Floppy &Hard Drive • Looking Ahead to … • Device Management • Process Management • Project Status

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