1 / 22

Adders

Adders. Binary Adders. Arithmetic circuit Addition Subtraction Division Multiplication. 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 10. One bit in sum. Two bit in sum. Half Adder. A combinational circuit that performs the addition of two bits. Two inputs and two outputs.

kevina
Download Presentation

Adders

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Adders

  2. Binary Adders • Arithmetic circuit • Addition • Subtraction • Division • Multiplication

  3. 0 + 0 = 0 • 0 + 1 = 1 • 1 + 0 = 1 • 1 + 1 = 10 One bit in sum Two bit in sum

  4. Half Adder • A combinational circuit that performs the addition of two bits. • Two inputs and two outputs. • Augend and Addend • Sum and Carry

  5. Truth table of Half Adder

  6. Circuit Diagram

  7. Full Adder • A combinational circuit that performs the addition of three input bits. • Three inputs and two outputs. • Sum and Carry

  8. Truth table of Full Adder

  9. Circuit Diagram

  10. Binary Ripple Carry Adder • Adders connected in cascade. • Carry output from one full adder connected to carry input of next full adder.

  11. Binary Ripple Carry Adder

  12. Input carry 0110 • A 1011 • B 0011 • Sum 1110 • Output carry 0011

  13. Input carry in the least significant position is 0. • Simple in concept. • Long circuit delay. • Many gates in the carry path.

  14. Why a Carry Lookahead Adder? • Practical design with reduced delay. • For a n- bit ripple carry adder • The longest delay path is 2n + 2. • 16 – bit ripple carry adder - delay is 34 gate delays

  15. Carry Lookahead Adder • Designed by a transformation of the ripple carry adder design in which the carry logic over fixed groups of bits of the adder is reduced to two-level logic.

  16. Design • OR gate and one of the AND gates are removed to form each of the full adders to form the ripple carry adder. • Separate the parts of full adders not involving the carry propagation path from those containing the path. • First part of each full adder • partial full adder - PFA

  17. Two outputs • Pi and Gi • From each PFA to ripple carry path • One input • Ci • From the carry path to each PFA

  18. Pi = Ai XOR Bi - Propagate function • Gi = Ai . Bi - Generate function

  19. WheneverPi = 1 • Incoming carry is propagated through bit position from Ci+1. • WheneverPi = 0 • carry propagation through bit position is blocked.

  20. WheneverGi = 1 • Carry output from the position is 1. • Regardless of value of Pi. • A Carry has been generated. • WheneverGi = 0 • carry is not generated. • Ci+1 is 0. • Ci is also 0.

  21. Generate and propagate functions correspond exactly to the half adder. • Essential in controling the values in ripple carry path. • PFA generates sum function by XOR of incoming carry, Ciand propagate function, Pi.

More Related