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Radiation Hard silicon sensors for the CBM experiment at FAIR

Radiation Hard silicon sensors for the CBM experiment at FAIR. Sudeep Chatterji CBM Group GSI Helmholtz Centre for Heavy Ion Research CBM Collaboration Meeting 9-13 th March, 2009. Outline. Need for Detector simulations Simulation packages being used Grid Optimization

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Radiation Hard silicon sensors for the CBM experiment at FAIR

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  1. Radiation Hard silicon sensors for the CBM experiment at FAIR Sudeep Chatterji CBM Group GSI Helmholtz Centre for Heavy Ion Research CBM Collaboration Meeting 9-13th March, 2009

  2. Outline • Need for Detector simulations • Simulation packages being used • Grid Optimization • Optimization of process parameters • Optimization of device parameters • Choice of Wafer Resistivity • Guard Ring Optimization • Capacitance (Backplane & interstrip)/Orientation • Radiation Damage Studies • Commercially available 3-D packages • Future Plans

  3. CBM STS Layout 8 low-mass micro-strip stations located in a dipole magnet STS: 8 low-mass micro-strip station

  4. STS – station #8 CBM — Radiation environment Neutron fluence in CBM cave Neutron fluence through Silicon Tracking System UrQMD + FLUKA simulation, 25 GeV Au beam on Au target a.u. 1-MeV neq /cm2/year STS beam aperture MUCH Typical operation scenario: 6 years  up to 1015 neq/cm2  radiation hardness regime of LHC/SuperLHC experiments

  5. Steps in Planar fabrication process • Fabrication Steps: • Initial Oxidation • p+ lithography • Oxidation for screen oxide • Re-expose p+ mask • Implantation of Boron for p+ strips and guard rings • n+ implant at the backside • Annealing • Front Metallization • Metal lithography • Metal Sintering at 4500 C • Passivation • Using Process Simulation we can simulate optimized • processing conditions like Implantation energy, • Ion Dose and Annealing temperature. • The output from process simulation package can be • fed as input file to device simulation package to extract • electrical characteristics like Breakdown Voltage • (VBD), Electric field, Potential, Capacitance and • Full Depletion Voltage (VFD).

  6. Packages being used/Limitations • SUPREM-4 & PISCES by Stanford University • SUPREM-4 is a Process simulator • (http://mems.mirc.gatech.edu/ece4752/suprem.html) • PISCES 2B is a 2D Device simulator • (http://home.comcast.net/~johnfaricelli/tcad.htm) • For graphical interface Postmini being used • Commercial versions of SUPREM and PISCES codes • available on Synopsis (former Avant Corp.), Silvaco and • Crosslight. • Crosslight provides free trial version for a period of two • months. • Limitation of grid points in SUPREM & PISCES • Problems while transferring structure file from SUPREM to • PISCES

  7. Simulation Grid Optimization • A good mesh is crucial to accurate simulation results. • Creating a good mesh comes from experience. • Primary goal of grid generation is to achieve • accurate simulation results with minimum simulation • time. • A coarse mesh implies less simulation time but less • accuracy. • A fine mesh increases accuracy at the expense of • time. • A grid should have max. node points where gradient • of physical quantitites (like potential, field) are • highest. • The following regions should have very fine mesh: • Around Junctions • Areas of high electric field (like curvatures) • At the interface of two regions (like Si-O interface) • Solution time α (mesh points)1.5-2.5 • Simulation works by solving basic semiconductor equations like Poisson's equation. continuity equation at each of the grid points.

  8. Device for Simulation (Single sided) XJ = 3.5 mm WN+ = 3.0 mm P+ Conc. = 5e19 /cm3 Substrate Conc. = 1e12 /cm3 tox = 1.6 mm tcp = 0.3 mm

  9. PISCES Simulation Grid

  10. Junction Curvature Effect 2-D Leakage Current Distribution at Breakdown

  11. Junction Curvature Effect 3-D Electric Field Distribution at Breakdown

  12. Optimization of process parameters

  13. Radiation Damage • Bulk Damage in Silicon is mainly caused by NIEL interaction of primary • particle with a lattice displacing a Primary Knock-on Atom (PKA). • The major effect expected from bulk damage is the change in the effective • carrier concentration (Neff) leading to Type Inversion. • The change in Neff is parameterized using Hamburg model: • For high quality oxide, the value of surface oxide charge (Qf) is expected • to be 3e11cm-2 (for non-irradiated detector) while after irradiation Qf • increases and saturates at about 1e12 cm-2.

  14. Variation of VFD with Fluence

  15. Wafer Resistivity • Lower resistivity silicon undergoes type-inversion at a higher fluence. • It however requires a high value of bias voltage at the start.

  16. Crystal Orientation • Three Crystal Orientation 111,100 & 110. • 100 beneficial in reducing the Interstrip Capacitance. • CTot = Cback + 2 X (C'int + C"int) • For large strip pitch, CTot dominated by Cback & there is no • advantage to use <100> orientation. • However for CBM STS (50 mm Pitch), Cint is dominating & • hence the possibility of using <100> orientation.

  17. Capacitance Values from Simulation • For comparable W/P ratio, Cint dominates over CBack.

  18. Effect of Orientation on CInt • Geometry File transferred from SUPREM to PISCES. • SUPREM can't simulate real structure for device analysis.

  19. Impact of W/P on VBD • VBD increases as W/P ratio becomes comparable.

  20. Device for Guard Ring Simulation

  21. Guard Ring spacing Optimization

  22. 3D Device simulations current research topic Simulation tools: • Silvaco (ATLAS and ATHENA) • Synopsis (Sentaurus Process and Device simulation). Advanced TCAD Bundle (ISE-TCAD used by HEP). At GSI through Europractice. Applications: BTeV and LHCb, http://phy.syr.edu/~jwang/projects/system_adm/tcad.html • D. Pennicard et.al., Simulation Results From Double-Sided 3-D Detectors, IEEE Trans.Nucl.Sci. Vol.54(4),1435-1443, 2007 • H.J. Kim, A Simulation study of double side silicon strip detector for the GLC intermediate tracker, 6th ACFA workshop, http://www.tifr.res.in/~acfa6/talks/par1-new/dssd_simulation.ppt • Y.K.Choi, A simulation study and design of the double-sided silicon microstrip detector, APPI 2005, Iwate, Japan, http://acfahep.kek.jp/appi/2005/TPs/choi@appi2005.pdf

  23. Summary/Future Plans • Simulations done for single sided strip detectors • 3-D simulation packages ordered (Synopsis) • Plan to install ISE-TCAD on CBM Server • Plan to study radiation damage in DSSDs • Plan to carry out annealing studies on Fz, DOFz, • Cz and MCz silicon before and after irradiation • Plan to work closely with CiS Institut für • Mikrosensorik Thanks a lot

  24. Backup Slides

  25. 1-D Boron Diffusion Profile

  26. Optimization of process parameters

  27. Radiation Damage

  28. Impact of Guard Ring on VBD

  29. Synopsis from EuroPractise S/W • Price: Advanced TCAD Bundle (Product Code: 4436-0) • 1 License:450 Euros (One Time)+1500 Euros (Per Year) • 20 License:2000 Euros (One Time)+1500 Euros (Per • Year) • No Support from SYNOPSIS

  30. List of Tools in TCAD Bundle

  31. Guard Ring spacing Optimization

  32. Thickness of Back Implant • Thickness of Back Implant > 2.5 mm

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