SMP Team

3. SMP Team

4. Menu Introduction B. Todd Hardware M. Kwiatkowski Testing and Testers S. Gabourin Software I. Romera User Interface M. Audrain Status & Future I. Romera

5. SMP 3v0 Introduction

6. SMP 3v0 - Introduction afe achine arameters P S M receives accelerator information generates flags & values directly transmitted and / or broadcast injection procedure protection configuration Beam Interlocks Collimation Beam Loss Monitors … Extraction Interlocks *fast *safe *reliable *available CERN = System Safety

7. Two Controllers

8. SPS Parameters

9. SPS Probe Beam Flag Fail-Safe = FALSE Fail-Safe = 1.6777215e15

10. SPS Setup Beam Flag Fail-Safe = FALSE Fail-Safe = 6.5535e14

11. Probe / Setup Timing

12. SPS Energy Flags Fail-Safe = FALSE Fail-Safe = 524.280 GeV

13. SPS Energy Flags

14. SPS Energy Flags

15. LHC Parameters

16. LHC Energy Fail-Safe = 7864.200 GeV

17. LHC Intensity Fail-Safe = 1.6777215e15 Fail-Safe = 6.5535e14

18. LHC Set-up Beam Flag

19. LHC Set-up Beam Flag Fail-Safe = FALSE

20. LHC Set-up Beam Flag

21. LHC Beam Presence Flag

22. LHC Beam Presence Flag Fail-Safe = FALSE

23. Squeezing Factors Fail-Safe = 0m

24. Moveable Devices and Stable Beams

25. Moveable Devices and Stable Beams Operator: <10 GeV window between LIMITs

26. Moveable Devices and Stable Beams

27. Moveable Devices and Stable Beams Operator: <1m window between LIMITs

28. Moveable Devices and Stable Beams

29. Moveable Devices and Stable Beams

30. Dependable Electronics Basis

31. VME Chassis & Generic Circuit - CISX Receiver – CISR Generator LHC – CISGL or Generator SPS – CISGS Arbiter – CISA

32. VME Chassis & Generic Circuit - CISX Monitor FPGA Receiver – CISR Generator LHC – CISGL Generator SPS – CISGS Arbiter – CISA Control FPGA VHDL implementation Safety approach?

33. Hardware Dependable Design

34. Design flow

35. Requirements Requirements requested by operators and/orapproved by MPP. E.G. Set-up Beam Flag equation normal relaxed very relaxed ion 36

36. Specification and formalisation vs English language formal language English + diagrams predicate logic Unlike the English, there is only one way to understand formal language.

37. Specification and formalisation vs English language formal language English + diagrams predicate logic Unlike the English, there is only one way to understand formal language.

38. Functionalblocks 39

39. Design flow

40. Implementation VHDL is not a programming language. It is a Hardware Description Language Mustunderstand expected synthesis result comments and naming convention important for the code review Critical code = strict Non-Critical code = engineer has freedom High % code reuse

41. Design flow

42. Simulation Unit Under Test Bus Functional Model Register Transfer Level

43. Simulation Test-bench= software wrapped around model response should be correct for all stimulus Simulationtoolcanexaminecodecoverage

44. Design flow

45. Hardware tester DeviceUnder Test

46. Hardware tester similar to simulation but real hardware Hardware response should be correct for each stimulus embedded logic analyzers provided by FPGA vendors Chip Scope, SignalTap, …

47. Hardware tester vs. simulation Complementary Software simulation: Hardware tester: source code tracking real time code coverage real distortions

48. Hardware Dependable Design Summary Our approach – dependable PLD designgoes on top of dependable electronics design formalisation of the specification split critical – non-critical reduction to minimum function exhaustive source code simulation full code coverage hardware testers code reviews external reviews

49. System Testing & Testers The “V” Approach

50. SMP Development: the “V” approach English Specification used for the Tester Determine Tests needed to verify each function Developed Independently of Controller Validation of Controller versus Tester versus English Specification V 51