UNIT - I I C Fabrication Technology

1. UNIT - IIC Fabrication Technology

2. Outlines • Chip-Making Process • Photolithography • CMOS IC Fabrication Processes • Simple Process • Packaging Technology

3. Packaging Crystal Growth Chip-Making Process: An Overview Photolithography

4. From Smithsonian, 2000 Growing the Silicon Ingot • Most common technique is the Czochralski (CZ) method developed by Mitsubishi Materials Silicon in the 50’s • Length: up to 2 m • Diameter: 200 mm (8”) to 300 mm (12”) • Weight: Over 225 kg. • Pulling takes up to hundred hours

5. Develop by Mitsubishi in the 50’s Czochralski (CZ) Method • Crystal orientation is determined by seed orientation • Ingot diameter is determined by temperature, orientation, and extraction speed. 1420 C

6. Ingot is cut around and ground down into a uniform diameter (8”-12”), then sliced into wafers of about 1 mm thick. Wire Saw Machine The sliced wafers are mechanically lapped by the use of alumina abrasive material to remove surface roughness and damages caused by the saw cut and to improve the flatness of the wafer. Lapping Machine Wafer Shaping

7. Mechanical damages induced during the previous processes are removed by chemical etching. The mechano-chemical polishing process improves the flatness of the wafer, making highly flat surface by the use of colloidal silica. Wafer Polishers Wafer Shaping (2)

8. N Well V DD V DD PMOS 2l PMOS Contacts In Out Out In Metal 1 NMOS Polysilicon Layout Schemetic NMOS GND The Target: CMOS Inverter

9. Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers CMOS Process at a Glance • One full photolithography sequence per layer (mask) • Built (roughly) from the bottom up 5 metal 2 4 metal 1 2 polysilicon 3 source and drain diffusions • 1tubs (aka wells, active areas)

10. Outlines • Chip-Making Process • Photolithography • CMOS IC Fabrication Processes • Simple Process • Packaging Technology

11. Photolithography • An IC consists of several layers of material that are manufactured in successive steps. Photo + Litho + Graphy (Light) (Stone) (Writing) =“Writing Stone with Light” • Photolithographyis used to selectively process the layers, where the 2-D mask geometry is copied on the surface.

12. oxide growth photoresist coating Photolithographic Process optical mask stepper exposure photoresist removal (ashing) Typical operations in a single photolithographic process process step Ion implantation Plasma etching Metal deposition photoresist development acid etch spin, rinse, dry

13. Oxide Growth/Oxide Deposition • Oxidation of the silicon surface creates a SiO2 layer that acts as an insulator. • Oxide layers are also used to isolate metal interconnections. An annealing step is required to restore the crystal structure after thermal oxidation.

14. Photoresist Deposition/Coating • The surface of the wafer is coated with a photosensitive material, the photoresist. • The mask pattern is developed on the photoresist, with UV light exposure. • Depending on the type of the photoresist (negative or positive), the exposed or unexposed parts of the photoresist change their property and become resistant to certain types of solvents.

15. A Mask Sample Stepper Exposure • Glass Mask (reticle) containing the patterns to be transferred is brought in close proximity to the wafer • The mask pattern is developed on the photoresist, with UV light exposure.

16. Photoresist Devolopment • The wafers are developed in either an acid or base solution to remove the nonexposed (exposed) areas of the photoresist. • Once the exposed photoresist is removed, the wafer is “soft baked” at a low temperature to harden the photoresist.

17. Etching is a common process to pattern material on the surface. Once the desired shape is patterned with photoresist, the unprotected areas are etched away. Acid Etching

18. Spin, Rinse, and Dry • A special tool called SRD is used to clean the wafers after each acid etch step • Use de-ionized water to remove any residue chemical substance. • Use nitrogen because it has no reaction with the silicon.

19. Ashing - Photoresist Removal • A high-temperature plasma is used to selectively remove the remaining photoresist without damaging previous layers. • After ashing the wafer is ready for the next round of photolithography.

20. Si-substrate UV-light Patterned optical mask Silicon base material Exposed resist SiO2 Si-substrate Si-substrate 3. Stepper exposure 1. After oxidation heat Exposed resist Photoresist SiO2 Si-substrate Si-substrate 4. Photoresist Devolop and Bake 2. After deposition of negative photoresist Photolithographic Process Example

21. Chemical or plasma etch Hardened resist SiO 2 Si-substrate 5. After development and etching of resist, chemical or plasma etch of SiO2 Hardened resist SiO2 Si-substrate SiO2 6. After etching and spin, rinse and dry. Si-substrate 8. Final result after removal of resist (ashing) Photolithographic Process Example • Step 7 is optional in this example. The step is need only in implanting a well or doping polysilicon • Planarization step is applied at least once in a cycle of photolithography

22. Diffusion:Wafer is exposed to gas containing dopant under high temperature (900-1100 C) 1000 C Ion Implantation:A beam of dopant ions is swept over the surface - causing damage to substrate, need annealing Purified Ion beam Diffusion and Ion Implantation • Change the electrical characteristics of silicon locally by adding doping agents to the exposed area. • The dopant ions penetrate the surface with a penetration depth that is proportional to their kinetic energy.

23. Outlines • Chip-Making Process • Photolithography • CMOS IC Fabrication Processes • Simple Process • Packaging Technology

24. Photolithography Masks • Each photolithography step during fabrication must be defined by a separate photolithography mask. • Each mask layer must be drawn (either manually or using a design automation tool) according to the layout design rules. • The combination (superposition) of all necessary mask layers completely defines the circuit to be fabricated.

25. Layout Design Rules • To allow reliable fabrication of each structure, the mask layers must conform to a set of geometric layout design rules. • Usually, the rules (for example: minimum distance and/or separation between layers) are expressed as multiples of a scaling factor - • lambda () - minimum resolution of a technology • For each different fabrication technology, lambda factor can be different.

26. Examples of Layout Design Rules A Minimum-Sized Transistor

27. Outlines • Chip-Making Process • Photolithography • CMOS IC Fabrication Processes • Simple Process • Packaging Technology

28. Packaging Technology • Many high-performance chips failed stringent test specifications after packaging because the designer (usually novice!) have not included various effects of packaging constraints and parasitics into their designs. • Ground planes, power planes, and bonding pads greatly affect the behavior of on-chip power and ground bus. • Length of bonding wire and lead length in a package generate a voltage drop in the output circuit. • Inappropriate type of package body can cause thermal runaway and hence damage the ICs.

29. Packaging Requirements • Electrical: Low parasitics • Low capacitance and Inductance • Mechanical: Reliable and robust • Moisture-proof • High pin density • Thermal: Efficient heat removal • High thermal conductivity • Low thermal expansion coefficient • Economical: Cheap

30. Package Types DIP - Dual-In-Line Pin QFP - Quad Flat Pack PGA - Pin Grid Array