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Advanced Reliable Systems Lab - VLSI Subsystem Design

This chapter focuses on the design of VLSI subsystems, specifically datapath operators and control structures. The Advanced Reliable Systems Lab at National Central University in Taiwan provides insights into the different categories of components and their tradeoffs in terms of speed, density, programmability, and ease of design.

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Advanced Reliable Systems Lab - VLSI Subsystem Design

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  1. Chapter3 VLSISubsystemDesign Jin-FuLi AdvancedReliableSystems(ARES) Laboratory DepartmentofElectricalEngineering NationalCentralUniversity Jhongli,Taiwan

  2. Outline Introduction DatapathOperators ControlStructures Advanced ReliableSystems(ARES)Lab.

  3. System-Level Hierarchy System(Top) Complexunits(cores) SimpleComponents Logic Circuits Silicon Advanced ReliableSystems(ARES)Lab.

  4. Categories of Components • Types ofdigitalcomponent • Datapathoperators • Memory elements • Controlstructures • I/Ocells • Tradeoffofselection • Speed • Density • Programmability • Easyofdesign • etc Advanced ReliableSystems(ARES)Lab.

  5. Datapath– Adder AdderTruthTable C A B A.B(G) A+B(P) A B SUM CARRY A B Generate SignalG(A.B):occurs whenacarry output(CARRY) G P C CARRY is internallygeneratedwithinthe adder. SUM Propagate SignalP(A+B): whenitis true,thecarry insignalC is passed tothecarry output(CARRY)whenC is true Advanced ReliableSystems(ARES)Lab.

  6. Datapath– Adder SUM=A B C CARRY=AB+AC+BC Single-bitschematicofSUM A B C A -C C -A -B B -A C -A B A SUM A -B -A -C A SUM Advanced ReliableSystems(ARES)Lab.

  7. Datapath– Adder Single-bitschematicofCARRY A B C A B CARRY CARRY -C -A -B Advanced ReliableSystems(ARES)Lab.

  8. Datapath– Adder Optimizedcombinationaladderschematic Ci+1=AiBi+AiCi+BiCi Si=(Ai+Bi+Ci).Ci+1+AiBiCi Vdd Ai Bi Ci Ci+1 Ci+1 Si S i Ci Bi Ai Vss Advanced ReliableSystems(ARES)Lab.

  9. Datapath– Adder Symmetricaloptimizedcombinationaladderschematic A B A A B A B Ci B CoutCout Ci S B A Ci B A Ci A B B A Advanced ReliableSystems(ARES)Lab.

  10. Datapath– Bit-ParallelAdder Paralleladderimplementations C<n+1> C<n+1> B<n> A<n> B<n> A<n> S<n> S<n> C<n> C<n> C<3> C<3> B<3> B<3> S<3> S<3> A<3> B<2> A<2> B<1> A<1> B<0> A<0> A<3> B<2> A<2> B<1> A<1> B<0> A<0> S<2> S<2> S<1> S<1> S<0> S<0> Cin Cin Advanced ReliableSystems(ARES)Lab.

  11. Datapath– Bit-ParallelAdder C<3> C<3> B<3> B<3> A<3> B<2> A<2> B<1> S<3> S<3> A<3> B<2> S<2> S<2> A<2> B<1> S<1> S<1> A<1> A<1> B<0> A<0> B<0> S<0> S<0> A<0> Vdd Subtract If (Subtract==0) {S=A+B;} else A-B {S=A-B;} Advanced ReliableSystems(ARES)Lab.

  12. Datapath– Bit-SerialAdder Cout 0110 A 01101 addend 110 Result 1001011011001 0 01001 B 001 0110 augend Cin Advanced ReliableSystems(ARES)Lab.

  13. Datapath– Carry Look-Ahead Adder (CLA) Objective Toavoid thelineargrowthofthecarrydelay, we useaCarryLook-AheadAdder(CLA)inwhich the carriescanbe generatedin parallel Feature TheCarryofeachbitisgenerated fromthepropagateandthegeneratesignalsaswellastheinputcarry The propagate andthegenerate signalsare derived fromthe operandAiandBiby Gi=Ai.Bi Pi=Ai+Bi Advanced ReliableSystems(ARES)Lab.

  14. Datapath– Carry Look-Ahead Adder Ci+1=AiBi+(Ai+Bi)Ci=Gi+PiCi C1=G0+P0C0 C2=G1+P1G0+P1P0C0 C3=G2+P2G1+P2P1G0+P2P1P0C0 C4=G3+P3G2+P3P2G1+P3P2P1G0+P3P2P1P0C0 C0 P0 G0 P0-P1G0-G1 P0-P2G0-G2 P0-P3 G0-G3 4-bit CLA CLG1 CLG2 CLG3 CLG4 C1 C2 C3 C4 SG1 SG2 SG3 SG4 S0 S1 S2 S3 Advanced ReliableSystems(ARES)Lab.

  15. Datapath– Carry Look-Ahead Adder CLG1 C0 P0 G0 C0 P0 C1 G0 G0 P0 G0 C0 C1 P0 Advanced ReliableSystems(ARES)Lab.

  16. Datapath– Carry Look-Ahead Adder CLG4 G3 G2 G1 G0 C0 C4 P0 P1 P2 P3 C4=G3+P3G2+P3P2G1+P3P2P1G0+P3P2P1P0C0 Advanced ReliableSystems(ARES)Lab.

  17. Datapath– Carry Look-Ahead Adder ManchesterCarryChain Ci+1=Gi+PiCi Gi=Ai.Bi Pi=Ai+Bi Introducethecarry-killbitKi, this termgets its namefromthefactthat if Ki=1,then Pi =0andGi=0,sothat Ci+1=0; Ki=1thus “kills” thecarry-out bit. Pi Gi Ci+1 Ci Ki Advanced ReliableSystems(ARES)Lab.

  18. Datapath– Carry Look-Ahead Adder Manchestercircuitstyles Pi Pi Gi Ci+1 Ci C C i+1 i Gi Pi Staticcircuit G i Clk Dynamiccircuit Clk P0 P1 P3 P2 C 4 C0 G0 G1 G2 G3 Clk DynamicManchesterchain C4 C3 C2 C1 Advanced ReliableSystems(ARES)Lab.

  19. Datapath– Carry Look-Ahead Adder Extensiontowideadders Ifweuseabrute-forceapproachforan8-bitdesign,thenthe carry-outbitC8 wouldhaveatermoftheform P7P6P5P4P3P2P1P0C0 MultilevelCLAnetworkscanimprovethisproblem bit[n-1] bit[0] n-bit adder [i+3] [i] 4-bit CLG Advanced ReliableSystems(ARES)Lab.

  20. Datapath– Carry Look-Ahead Adder Pi+3 Gi+3 Pi+2 Gi+2 Pi+1 Gi+1 Pi Gi blockpropagate P[i,i+3] G[i,i+3] blockgenerate 4-bit CarryLookaheadGenerator Ci+3 Ci+2 Ci+1 G[i,i+3]=Gi+3+Pi+3Gi+2+Pi+3Pi+2Gi+1+Pi+3Pi+2Pi+1Gi P[i,i+3]=Pi+3Pi+2Pi+1Pi Advanced ReliableSystems(ARES)Lab.

  21. Datapath– Carry-SkipAdder Acarry-skipadderisdesignedtospeedupawideadderbyaiding thepropagationofacarrybitaroundaportionoftheentireadder. [i+3] [i] ci ci ci+k ci+4 4-bit adder k-bit adder P[i,i+3] Carry-skip ci+4+ci.P[i,i+3] Carry-skiplogic Generalization P[i,i+3]=Pi+3Pi+2Pi+1Pi Carry=Ci+4+P[i,i+3]Ci Advanced ReliableSystems(ARES)Lab.

  22. Datapath– Carry-SelectAdder b7a7 b6a6b5a5 4-bit adderU1 s6s5 b4a4 b7a7 b6a6b5a5 4-bit adderU0 s6s5 b4a4 c8 c8 c=1 c=0 s7 s4 s7 s4 b3a3 b2a2b1a1 4-bit adderL b0a0 1 0 1 0 1 0 1 0 1 0 MUX MUX MUX MUX MUX c4 c0 c8 s7 s6 s5 s4 Advanced ReliableSystems(ARES)Lab.

  23. Datapath– Conditional-SumAdder A0 B0 Conditional cell S0 S1 C0C1 A1 B1 Conditional cell S0 S1 C0C1 A2 B2 Conditional cell S0 S1 C0C1 A3 B3 Conditional cell S0 S1 C0C1 C0=Cin C4 S S S S 0 1 2 3 Advanced ReliableSystems(ARES)Lab.

  24. Datapath– 8-bitConditional-SumAdder Advanced ReliableSystems(ARES)Lab.

  25. Datapath– Multipliers Bit-levelmultiplier a b 0 0 0 1 1 0 1 1 axb 0 0 0 1 a b axb Multiplicationoftwo 4-bitwords a3b3 a2b2 a1b1 a0b0 a3b0a2b1a1b2a0b3 a2b0a1b1a0b2 a1b0a0b1 a0b0 a3b1a2b2a1b3 a3b2a2b3 a3b3 p7 p6 p5 p4 p3 p2 p1 p0 Advanced ReliableSystems(ARES)Lab.

  26. Datapath– Multipliers Theproductaxbis givenby the8-bitresult p=p7p6p5p4p3p2p1p0 Theith producttermpican be expressedas ajbk ci1 pi ijk Alternateviewofmultiplicationprocess 0 (axb0)2 (axb1)21(axb2)22(axb3)23 (a3 a2 a1 a0)xb3 p7 p6 p5 p4 p3 p2 p1 p0 Advanced ReliableSystems(ARES)Lab.

  27. Datapath– Multipliers Usingaproductregisterformultiplication 6 5 4 3 2 1 0 Product register 7 (axb0)20 (axb1)21 (axb2)22(axb3)23 Advanced ReliableSystems(ARES)Lab.

  28. Datapath– Multipliers Shift-rightmultiplicationsequence a2b0a3b0 a0b0a1b0 a3b0 a1b0a2b0 add (axb0)shift right a0b0 a2b0a1b1 a3b0a2b1 a0b0 a3b0a2b1 a1b0a0b1 a2b0a1b1 cx a3b1 add (axb1)shift right a0b0 a1b0a0b1 cx a3b1 a2b0a1b1a0b2 a3b0a2b1a1b2 a0b0 a3b0a2b1a1b2 a1b0a0b1 a3b1a2b2 add (axb2)shift right cya3b2 a2b0a1b1a0b2 a0b0 a1b0a0b1 a3b1a2b2 cy a3b2 a2b0a1b1a0b2 a0b0 a3b0a2b1a1b2a0b3 a1b0a0b1 add (axb3)shift right a3b1a2b2a1b3 a3b2a2b3 p7 a3b3 Advanced ReliableSystems(ARES)Lab.

  29. Datapath– Register-BasedMultiplier Product register(2n) clk shr n Multiplier Multiplicand 0 n n MUX n n-bit adder n Advanced ReliableSystems(ARES)Lab.

  30. Datapath– Array Multipliers • Considertwo unsignedbinaryintegersX andY n1n1 Y j X i Y2j i X2 j0 i0 n1  n1 PXY X 2  i j i j Y2 i0 n1n1  i0j0 nn1 j0 ij (XY)2 i j   k 0 k P 2 k Advanced ReliableSystems(ARES)Lab.

  31. Datapath– Array Multipliers X3 X2 X1 X0 Y0 Y1 P0 Y2 P1 Y3 P2 P3 P5 P7 P6 P4 Advanced ReliableSystems(ARES)Lab.

  32. Datapath– Array Multipliers X3Y0 X1Y0 X0Y0 X2Y0 0 0 0 X1Y1 X0Y1 X2Y1 X3Y1 X1Y2 X0Y2 X2Y2 X3Y2 X1Y3 X0Y3 X2Y3 X3Y3 0 P7 P6 P3 P1 P0 P5 P4 P2 Advanced ReliableSystems(ARES)Lab.

  33. Datapath– BoothMultiplier Booth’s algorithmtakes advantages ofthefactthatanadder-substractorisnearlyasfastandsmallasa simpleadder Considerthe two’scomplementrepresentationofthemultipliery n1n2 y2 y 2 yn12 yn2 n  n Therepresentation canberewrittenas n1n2 y2(y y )2 (y y )2 (yn3yn2) n n1n n2 n1 Extractthefirsttwoterms n1 y2(y y)2 (y n1n • y ) • n2n1 n  Theright-handtermcanbe usedtoaddxto partial product The left-hand termadd2x Advanced ReliableSystems(ARES)Lab.

  34. Datapath– BoothMultiplier ActionsduringBoothmultiplication yi yi1yi2 Operation 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 Add0 Addx Addx Add2x Sub2x 1 0 1 1 1 1 1 0 1 Subx Subx Add0 Forexample,x=011001(2510),y=101110(-1810) 1. y1y0y-1=100,so P1=P0-2x.1=11111001110 2. y3y2y1=111,so P2=P1+0.4=11111001110 3. y5y4y3=101,so P3=P2-x.16=11000111110 Advanced ReliableSystems(ARES)Lab.

  35. Datapath– BoothMultiplier Structureofa Boothmultiplier left shift 2 Pj+2 Adder/substractor yi+4 yi+3 yi+2 code Mux sel Pj+1 x 2x Stagej+1 0 left shift 2 Pj+1 Adder/substractor yi+2 yi+1 yi code Mux sel Pj x 2x Stagej 0 Advanced ReliableSystems(ARES)Lab.

  36. Datapath– WallaceTreeMultiplier • AWallacetreeis a fulladdertree structured speciallyfora quickaddition ofthe partialproducts • Example • A16x16Boothmultiplier • 8 partialproductsaregenerated • Assumethatall partialproductsarenegativesoall sign extension bitsare1’s • Sign extensioncorrectionvectoris 1010101010101011 • 1111111111111111 • 11111111111111 • 111111111111 • 1111111111 • 11111111 • 111111 • 1111 • 11 • 1010101010101011 Advanced ReliableSystems(ARES)Lab.

  37. Datapath– WallaceTreeMultiplier Wallacetreemultiplication Partial Products 1ststage 4-2compression 2nd stage 4-2compression 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 Sign Extension Correction FinalAddition Advanced ReliableSystems(ARES)Lab.

  38. Datapath– WallaceTreeMultiplier Inputs Inputs FA FA c s c s C Cin Cin out FA FA FA Cout FA FA c s c s Outputs Outputs 4-2compressor Carry-saveadder Advanced ReliableSystems(ARES)Lab.

  39. Datapath– SerialMultiplication Serialmultiplier reset serialregister X Y 1. RequireMNclockcycles toproduceaproductforanN-bit multiplier anda M-bitmultiplicand Advanced ReliableSystems(ARES)Lab.

  40. Datapath– SerialMultiplication Serial/parallelmultiplier Y0Y1 Y2 Y3 X D D D S0 S1 S2 D D D RequireM+Nclockcycles toproduceaproductforanN-bit multiplierandaM-bitmultiplicand Thecriticalpathconsistsoftheadders Advanced ReliableSystems(ARES)Lab.

  41. Control– FSM Moore input clk Mealy output input clk output Advanced ReliableSystems(ARES)Lab.

  42. Control– FSM • FSM designprocedure • Drawthestate-transitiondiagram • Checkthestatediagram • Writestateequations(WriteHDL) • An exampleof state-transitiondiagram • R IDLE IDLE:(S1,S0)=(00) WAIT:(S1,S0)=(01) EXIT:(S1,S0)=(10) A:car-in C:change-okR:rst -A A -A EXIT WAIT C -C A Advanced ReliableSystems(ARES)Lab.

  43. Control– FSM Check the state-transitiondiagram Ensure allstates arerepresented,includingtheIDLE state Check thattheORofalltransitionsleavingastateis TRUE.Thisis asimplemethodofdeterminingthat thereis awayoutofastateonceentered. Verifythatthe pairwiseXORofallexittransitionsis TRUE.Thisensures thattherearenotconflictingconditionsthatwouldleadtomorethan oneexit- transitionbecomingactive atanytime. Insertloopsintoanystateifitisnotguaranteedto otherwise changeoneachcycle. FormalFSMverificationmethod Performconformancechecking Advanced ReliableSystems(ARES)Lab.

  44. Control– VerilogCoding Stylefor FSMs module toll_booth(clk,rst,car_in,change_ok,green); EXIT:if(car_in==1’1)begin next_state=EXIT; green=1’b1; endelsebegin next_state=IDEL; green=1’b0; end default:begin next_state=IDLE; green=1’b0; end input clk,rst,car_in,change_ok; green; state_reg,next_state; output reg[1:0] parameterIDLE =2’b00; parameterWAIT=2’b01; parameterEXIT =2’b11; always@(posedgeclkorposedgerst)begin If(rst==1’b1)state_reg<=IDLE; elsestate_reg<=next_state; end always@(state_regorcar_inorchange_ok) begin endcase end case(state_reg): IDLE:if(car_in==1’1)begin next_state=WAIT; green=1’b0; endelsebegin next_state=IDEL; end WAIT:if(change==1’b1)begin next_state=EXIT; green=1’b1; endelsebegin next_state=WAIT; green=1’b0; end endmodule Advanced ReliableSystems(ARES)Lab.

  45. Control– PLA StructureofaPLA Minterms ANDarray ORarray f0 f1 f2 f3 a b c d APLArepresentsanexpressionofsum-of-product(SOP) fimi(a,b,c,d) i f1abcdabcdabcd Advanced ReliableSystems(ARES)Lab.

  46. Control– PLA Fuse-programmablePLA Fuse f0 Jin-FuLi, EE,NCU f1 f2 f3 a b c d Advanced ReliableSystems(ARES)Lab.

  47. Control– PLA Logic gate diagramofa PLA f0 Jin-FuLi, EE,NCU f1 f2 f3 a b c d Advanced ReliableSystems(ARES)Lab.

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