Enhancing Availability of Xilinx FPGA in Orbit: Analysis & Solutions

1. Availability Analysis of Xilinx FPGA on Orbit Nozomu Nishinaga National Institute of Information and Communications Technology Masayoshi Yoneda NEC TOSHIBA Space Systems, Ltd. MAPLD2005

2. Outline • Motivation • Heavy Ion test results of Virtex II pro • Availability analysis • Conclusion MAPLD2005

3. Motivation • Very high availability or low non-availability is required for the consumer communications equipment. • typical non-availability value for terrestrial network equipment is 10E-6 • If the SEU can be defined as an accidental failure and the failure can be fixed without any loss of the original device function. • the rebooting process also can be defined as a repairing • Does equimpment with S-RAM type FPGAs meet the non-availability criteria? MAPLD2005

4. Radiation test of Virtex II Pro • Virtex II pro (XC2VP7-5FG456 and XC2VP4) • Test carried out in November 2003 and February 2004 at TIARA in Takasaki, Japan • Heavy Ions (N, Ne, and Kr) • Result compared with that of Virtex II. (Gary Swift, Candice Yui, and Carl Carmichael,” Single-Event Upset Susceptibility Testing of the Xilinx Virtex II FPGA,” MAPLD2002, paper P29) MAPLD2005

5. Devices Under Testing MAPLD2005

6. XC2VP4 XC2VP7 Virtex-II Radiation test result (1) 0.000001 0.0000001 1E-08 Cross Section [cm^2/bit] 1E-09 Block RAM region 1E-10 1E-11 0 10 20 30 40 50 60 70 LET[Mev cm^2/mg] MAPLD2005

7. Radiation test result (2) Configuration Memory region MAPLD2005

8. SEU frequency analysis (CREAM 96) XC2VP4 XC2VP7 MAPLD2005

9. Mean Time Before Failure Analysis • If the SEU can be considered as A Failure, the MTTR is roughly proportional to the size. • System MTBF -> Harmonic Mean of all functional blocks • Assumption 1: All the SEUs can be detected. • Assumption 2: All the gates are used. • Assumption 3: All the SEUs must be repaired as soon as quickly MAPLD2005

10. Mean Time To Repair (MTTR) • REBOOT == Repair • The effects of SEU are volatile. • By loading the correct configuration data, the operation mode will go to the normal mode. • Rebooting time -> Repair time • The maximum data rate for loading is fixed : 50M byte/Sec. for XC2VP series. • The larger gate size or configuration size, the longer MTTR becomes necessary. MAPLD2005

11. Triple Module Redundancy Case 1: One out of Three system failure is acceptable. • Loose regulation • Acceptable when the MTBF is quite large compared with MTTR Case 2: NO failure is acceptable • Tight configuration • The output is always guaranteed. MAPLD2005

12. Non-Availability Alalysis • MTBF is proportional to the area of the die and MTTR is also proportional. -> Large FPGA has disadvantage. • Large size FPGA does not meet the criteria 10e-6 • How to mitigate? – divide small FPGAs • Much larger down load rate will be needed (50 M Byte/S is too slow) MAPLD2005

13. Dividing • The Non-Availability depends on the size • A Large size FPGA is split up to several (D) small FPGAs • Sc-> Configuration data size [bits] • R -> Configuration rate [bps] MAPLD2005

14. Interstage VOTER • The availability is varying With or Without the interstage Voter. • The performance with interstage voters is superior to tat without the voters. MAPLD2005

15. Non-Availability Analysis with dividing Area or gate loss due to the division is not taking into account in this figure. -> next issue MAPLD2005

16. Conclusion • Non availability analysis for Vertex II pro • Large scaled FPGA do not meet a non availability criteria for communication equipment (10e-6). • Need much faster or wider Interface for configuration to enhance its availability. MAPLD2005