Xilinx/Exemplar Logic FPGA Synthesis Solution

Xilinx/Exemplar LogicFPGA Synthesis Solution

The Exemplar AdvantageTechnology Leadership • Goal: To provide a common methodology of powerful, flexible & integrated solutions for high density FPGAs & ASICs • Market Leadership • 2x revenue to the closest competition • 70% growth yr.-to-yr. • Over 15,000 seats, more than 5000 customers • Pioneered the concept of technology specific optimization for FPGAs

The Exemplar Product Line ($3.5K) ($7 - 10K) ($17.5K)

Xilinx-Exemplar AllianceCommitted Partnership delivers powerful solution! • Increased technical collaboration • Improve Q of R , Xilinx specific optimization, incremental optimization & ease of use • Joint technical publication • Methodology guide for reduced design time • Enhanced support • Cross training and certification program

Xilinx-Exemplar AdvantageGoal: Reduced Design time & Improved QOR • Powerful HDL Based Methodology • Inference(e.g. RAM), links to verification • Proper Design Management • Easy environment setup, hierarchical management • Constraint Based Optimization • maxdly, Clock_cycle,arrival_time • Integration with Xilinx Place & Route tools • via EDIF, SDF

Xilinx Optimization Technology • Generic Optimization • Timing Driven Synthesis • Resource Sharing • Xilinx Optimization • Optimization and Mapping to LUTs • RAM Inference • Modgen for: Multipliers, Adders, Subtractors, Comparators (e.g. Map to Carry logic for arithmetic functions) • TimeSpecs Embedded in EDIF netlist • Automatic global buffer insertion • Automatic GSR Inference • Complex IO Pad Mapping • Slew rate Control • Assign Pad Location

Xilinx RAM Inference from RTL RAM 32x8 address data_in data_out we I0 : process (we,address,mem,data_in) begin if (we = '1') then mem(conv_integer(address)) <= data_in ; end if ; data_out <= mem(conv_integer(address)) ; end process ; • RAM_DQ : • Synchronous,asynchronous • single-port • RAM_IO : • Synchronous,asynchronous • single-port • bi-directional data line

Xilinx Counter Inference from RTL architecture rtl of pl_counter is signal count : std_logic_vector (1 downto 0); begin count_it : process(clk,reset) begin if (reset = '1') then count <= "00" ; elsif (clk = '1' and clk'event) then if (load = ‘1’) then count <= data_in; else count <= count + "01"; end if; end process ; data_out <= count; end RTL ;

Automatic IO Insertion for Xilinx • IBUF & OBUF cells automatically applied to all I/O signals on top-level module • 4 BUFGP buffers automatically inserted on clock & high drive signals • Maps to complex Registered I/O’s cells (OUTFF, INFF) when possible

Technical Collaboration Better Future Products • Improvements to Q of R • Improvements to Place & Route run times • Addresses serious methodology issues • Simplifies overall design process by integration of place & route tools

Synthesis • Design Problems • Areas • Timing Violations • Routing Congestion • Netlist • ECO Place & Route Incremental Optimization • Incremental ECO Optimization • Incremental Timing Optimization • Synthesis tool can restructure logic, duplicate logic and replace operators • Design Modification capability build into Synthesis tool • Becomes part of repeatable script

Timing Analysis & Optimization • Timing Analysis based on wire load models • Constraint-Driven • Set constraints from GUI, script or file • Determine Timing Violations • Critical Path Retiming • Also use Modgen & Hierarchy Manipulation to achieve timing improvements

Graphical HDL Entry Error Cross Highlighting Synthesis Static Timing Analysis Place and Route Error Cross Highlighting Error Highlighting between Synthesis schematics, HDL code and Place & Route

Clock Constraint Comb. Logic D Q D Q Timespec Constraints Generated by Leonardo and Embedded in EDIF Netlist as properties Leonardo EDIF Netlist (instance ix41 (viewRef NETLIST (cellRef OBUF (libraryRef xi4xv )))) (instance ix29_ix6 (viewRef NETLIST (cellRef FDCE (libraryRef xi4xv ))) (property TNM (string "GROUP_0")) (property INIT (string "R"))) (instance ix29_ix9 (viewRef NETLIST (cellRef FDCE (libraryRef xi4xv ))) (property TNM (string "GROUP_0")) (property INIT (string "R"))) (instance ix51 (viewRef NETLIST (cellRef TIMESPEC (libraryRef xi4xv ))) (property TS1 (string "FROM:GROUP_0:TO:GROUP_0=4.76ns"))) (instance ix50 (viewRef NETLIST (cellRef EQN (libraryRef xi4xv ))) (property EQN (string "((I0*I1)+(~I0*~I1))")) (property area_add_report (string "1")) (property area_add_units (string "Packed CLBs"))) Generating Timespec Information

... Z<= A + B; ... Module Generation Hand-crafted Results! Maps directly to target technology Xilinx specific operators created using CY4 carry chain logic All arithmetic operators support signed & unsigned arithmetic A add_32 Z Choice Area Speed Runtime B add_32 Arch1 250 21nS 2s Arch2 390 15nS 3s Arch3 500 12nS 3s Arch4 650 6nS 4s Arch5 920 5nS 11s FPGA-Specific architectures FPGA vendor generators Operators Implemented by MODGEN

LeonardoHigh Control Optimization through Attributes Preserve Internal Signals and Signalnames Insert Internal clock Buffers

Timing Driven Synthesis • Clock Constraint • Clock Period • Multiple Clock Support • Multi-cycle paths • Support for false paths • Input Arrival Delay • Clock to Out Delay • New constraint editor in v5.0 • 5/98

Standard Effort Performs 4 Optimization Passes Best Results is used Each Pass Employs different Optimization Groups Best Pass Automatically Selected for each block of Hierarchical Designs Multi-Pass Optimization Quick Mode Performs 1 Optimization pass Based on Heuristics

Support for Bottom-up Design • Required for Gate Array Designs • Perform optimization on individual blocks and Top-level • No Load constraints on sub-blocks • Must perform top-level opt to insert I/O buffers and Reset circuit • LEONARDO {5} read -format edif A.edif B.edif C.edif • LEONARDO {6} read -format vhdl top.vhdl • LEONARDO {6} optimize -ta xi4xv -no_hier -area -chip

Hierarchy Manipulation Group LEONARDO{5} group B C -inst_name BC Ungroup LEONARDO{6} ungroup B

State Machine Optimization • Explicit State Machine Encoding (v4.2) • Template Coding Style • Re-encoding on the fly • Implicit State Machine Encoding (v5.0) • Recognizes state machine functionality from any coding style • Supports user defined encoding style • New FSM Optimizations (v5.0) • Dead State Analysis and removal • Unreachable State Analysis and removal

Summary • Overview of current features • Multipass Optimization • RAM Inference • Hierarchy Management • Module Generation • Future Development • Error Cross Highlighting • Incremental Optimization • Synthesis and Place & Route Integration

Xilinx/Exemplar Logic FPGA Synthesis Solution