Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design

SpezielleAnwendungen des VLSI – EntwurfsApplied VLSI design Speed Optimization Course and contest Results of Phase 5 Nam Pham Van

Someadderstructure

Design comparison (Synopsys) • Condition: • Supply voltage 1.2 V • All libraries were used (CORE65LPLVT, CORE65LPSVT, CORE65LPHVT)

Chosen design • Han Carlson Adder (a parallel prefix adder): • Combination of Brent Kung & Kogge Stone structure • One of the faster adder • Suitable for VLSI • A = 0.5 * n * log(n) • T = log2(n) + 1

How to achieve better speed performance?

At behavioral / design level • Improvement can be done with: • Pipelining  higher throughput • Array structures • Tree structures • Replication (parallelization) • Combinations of those

Delay investigation - example inverter • Low delay T with: • Lower capacitance C • Higher width W of the transistors (p-transistors 3x bigger than n-transistors)

Technology optimization • Propagation Delay T : tr: rise time • tf: fall time • T = (tr + tf) / 2Cl: capacitance • ß : unity gain • Vdd : supply voltage • W : width • L: length • Strategy: • Layout optimization  Cl • At the transistor level  ß ( W and L ) • Supply voltage  Vdd • 0

Voltage & Libraries comparison (Synopsys) Condition: All libraries (CORE65LPLVT, CORE65LPSVT, CORE65LPHVT) Condition: Supply Voltage 1.3 V

ASIC design – Cadence Encounter

Source • BehroozParhami; „Computer Arithmetic – Algorithms and Hardware Designs“, University of California • Reto Zimmermann; „Binary Adder Architectures for Cell-Based VLSI and their Synthesis“ • Prof. Dirk Timmermann; „SystemgerechteAlgorithmen“, „HochintegrierteSysteme I & II“, Universität Rostock

Thank you for your attention!

Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design