IP – Based Design Methodology

1. IP – Based Design Methodology Daniel D. Gajski University of California gajski@uci.edu http://www.ics.uci.edu/~gajski

2. Outline • Drivers of IP business • Obstacles to IP success • Possible solutions • Business models • Future

3. IP Drivers • Product complexity • Market pressure • Expertise shortage • Productivity gap • Business model

4. Solving Complexity / Productivity Problems IP 1. IP 2. 3. IP 4. IP

5. Obstacles to IP Success • Partially abstracted design process • Simulation based design flow • Simulation models are not easily synthesizable • IP definition (parameterization, verification, characterization) • IP-centric models for SOC • No separation of computation and communication • Need for encapsulation • Reuse automation • IP do not fit into past methodologies and tools • IP-centric methodology • No clearly defined business models • Volume, value-added and protection

6. Solving Complexity / Productivity Problems • Higher level of abstraction • Specification • Architecture • Communications • Components (IP) • Tools and methodologies • Standardization • Languages • Models • Protocols • Documentation (IP)

7. Simulation Based Design Flow • Simulatable but not synthesizable 3.415 2.715 case X is when X1 => when X2 => Finite State Machine Table Lookup Controller Memory

8. IP Definition • Quality, verification, characterization vs. parameterization Quality, Verifiability, Testability, Characterizability 1 single instance No. of parameters, Generality

9. RTL Specs x = 0 y = 0 ... S1 count = n S1 x = 0 y = 1 ... temp1 = a(i) + b(i) temp2 = c(i) + d(i) count = count - 1 S2 S2 Count ¹ 0 Count ¹ 0 x = 1 y = 0 ... S3 s(i) = temp1 * temp2 S3 Count = 0 Count = 0 FSM FSMD

10. Mem RF RF . . . . . . RTL Architectures Inputs Control Data Count D Q FF State reg. or PC Mem RF . . . Outputs +/- + D Q FF temp1 temp2 Input logic State reg. Ouput logic Controller Datapath Control Data Controller Processor (controller & datapath)

11. IP-centric Specs S1 Y variable A: array[1..20] of integer A D C Program ………….. ………….. ………….. ………….. ………….. ………….. B variable i, max: integer; max = 0; for i = 1 to 20 do if (A[i] > max) then max = A[i]; end if; end for; S2 e1 e2 C e3 S3 SFSMD Concurrent, hierarchical SFSMD

12. Mem RF RF IP IP Processor IP Ctrl Ctrl DP DP IP-centric Architecture Control IP SR/PC Processor IP IP temp1 temp2 Controller Datapath IP-centric processor IP-centric system

13. IP IP IP-Centric Models • Present • Future B T W C IP

14. replicable C C IP at any time virtual channel channel with IP protocol Reuse Explorations • Behavior IP PE replicable T IP at any time synthesizable behavior wrapped IP behavior transducer • Channel IP

15. Reuse Optimization (a) Two synthesizable behaviors connected by a channel • Wrapper Resolution A A B B C (b) Synthesizable behavior connected to an IP A A W IP IP (c) IP connected through an incompatible channel A T W C IP B T A T IP

16. CAD Methodology • Capture – Simulate (60’s – 80’s) • Describe – Synthesize (80’s – 00’s) • Specify-Explore-Refine (00’s – 20’s)

17. Past, Present and Future Capture & Simulate Describe & Synthesize Specify, Explore & Refine Executable Spec Functionality Specs Specs Algorithms (software) Algorithms Algorithms Connectivity Architecture Protocols Communications Describe Design Design Design Timing Logic Logic Logic Simulate Simulate Physical Physical Physical Manufacturing Manufacturing Manufacturing

18. Specs Algorithms (software) Describe Design Logic Simulate Physical Manufacturing Present and Future Issues Describe & Synthesize Specify, Explore & Refine Executable Spec Functionality Issues: IP vs EDA Semi’ vs. Systems Simulation vs. Synthesis Hardware vs. Software VHDL vs. C Top-down vs. Bottom-up Integrated vs. Outsourced CE vs. CS Algorithms Connectivity Architecture Protocols Communications Design Timing Logic Physical Manufacturing

19. Synthesis flow Analysis and validation flow Specification model Validation of algorithm and functionality Simulation model IP Estimation Validation of functionality and synchronization Architecture model Simulation model Estimation Communication synthesis IP Validation of functionality and communication Simulation model Communication model Estimation SW synthesis HW synthesis Simulation model Validation of timing and performance Implementation model Estimation Manufacturing SpecC Methodology Architecture exploration

20. Business Model Product, Knowledge System house IP Providers EDA vendors Design house Integrators Tools, Libraries Commodity IPs, Standard IPs, Star IPs Manufacturing Technology, Libraries

21. Business Model Product, Knowledge System house IP providers EDA vendors Design house Integrators Tools, Libraries, Commodity IPs, Standard IPs Star IPs Manufacturing Technology Scenario 1:Design world

22. Business Model Product, Knowledge System house Design house IP providers EDA vendors Integrators Tools Star IPs Manufacturing Technology, Libraries, Commodity IPs, Standard IPs Scenario 2:Split Design

23. Business Model Product, Knowledge, Assembly System house IP Providers EDA vendors Tools, Libraries Standard IPs, Star IPs, Commodity IPs Manufacturing Technology, Libraries Scenario 3:IP Providers World

24. Business Model Product, Knowledge System house IP providers EDA vendors Tools, Libraries, Commodity IPs, Standard IPs Star IPs Manufacturing Technology Scenario 4:Systems world

25. Top-down vs. Bottom-up Spec Spec Real Comp. (hard) Virtual Comp. (soft) Layout Layout Manuf. Manuf.

26. Reuse Paradigm • New Languages, guidelines, extensions • Models for exploration (spec, arch, comm, RTL) • Separation of computation & communication • Encapsulation • IP automation standards • Reuse automation (Synthesis with reuse) • IP-centric methodology

27. Conclusion