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SERENA Project: the kick off

SERENA Project: the kick off. SERENA Current schedule. SERENA LONG TERM PLAN. SERENA DOCUMENTATION. (see Released_doc annex). SERENA SYSTEM AIV. (see AIV_program_0.3 annex). SERENA SCU / SYSTEM. Outlook. I/Fs developing status DHSU Architecture System Budgets. SERENA SCU / SYSTEM.

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SERENA Project: the kick off

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  1. AMDL - Andrea M. Di Lellis SERENA Project: the kick off

  2. AMDL - Andrea M. Di Lellis SERENA Current schedule

  3. AMDL - Andrea M. Di Lellis SERENA LONG TERM PLAN

  4. AMDL - Andrea M. Di Lellis SERENA DOCUMENTATION (see Released_doc annex)

  5. AMDL - Andrea M. Di Lellis SERENA SYSTEM AIV (see AIV_program_0.3 annex)

  6. AMDL - Andrea M. Di Lellis SERENA SCU / SYSTEM Outlook • I/Fs developing status • DHSU Architecture • System Budgets

  7. AMDL - Andrea M. Di Lellis SERENA SCU / SYSTEM NPA-IS System PICAM 90°x 360° Main S/C Power Bus +28VDC SCU Limited PWR Bus 28 VDC Redu S/C Power Bus +28 VDC Unit 2 S pW 10 / (50) Mb/s LVDS Link ELENA / MIPA 1.8° x 76°/ 9°x 180° SCU L. PWR +28VDC S/C Spacewire SERENA Bus S/C OBDH NPA-IS SCU Electronics Unit- 1 (ELENA box)‏ Unit 3/4 Redu SpW Bus 2Mb/s RS-422 Link STROFIO 20° 20° FOV Unit 5 SCU Limited Power Bus 28 VDC S/C fixation platforms

  8. AMDL - Andrea M. Di Lellis SERENA SCU / SYSTEM I/Fs

  9. AMDL - Andrea M. Di Lellis Developing & Testing I/F 50 MHz OSC LocTM/LocTC Serial 2Mb/s I/F Drivers Transceiver ELENA I/F 3-Cube Compressor 3-Cube Power Switch LocTM/LocTC Serial 2Mb/s I/F Drivers MIPA I/F 3-EEPROM X X X X 2-EEPROM Transceiver LocTM/LocTC Serial 2Mb/s I/F Drivers EEPROM Power Switch 1-EEPROM 128kx8 with EDAC STROFIO I/F Leon-3 FT core courtesy By Gaisler Research TM PICAM I/F LocTM/LocTC Serial SpW I/F Drivers [A0..A16] EDAC 2x12 to16Recon- structor ACTEL RTAX2000S [D0..D24] SURV PROM 8kx16 PWR EN/DIS LINEs 1-SRAM 512kx8 with EDAC 2-SRAM 512kx8 with EDAC 3-SRAM 512kx8 with EDAC SPACEWIRE kernel ECSS-E-50-12 A POWER Control I/F TM/TC LVDS Transceivers Reset Circuitry +3.3V EMC FILTER DC / DC EMC FILTER Converter BP-MPO DHSU DPU, AMD - V1.0 Rev. C S/C SPACEWIRE TC/TM I/F S/C POWER I/F DHSU Block Diagram

  10. AMDL - Andrea M. Di Lellis SERENA I/Fs architecture LEON CORE AHB Interface AHB AMBA AHB Controller Timers IrqCtrl Memory AHB/APB Controller Bridge UARTs I/O Ports AMBA APB ELE Ser IF To SRAM I/F TO EEPROM I/F To COMPR I/F APB/Switch Bridge MIP Ser IF CFG Port STR Ser IF PIC SpW IF Main S/C SpW IF Legend: 2Mb/s I/F SCU SpW I/F Redu S/C SpW IF

  11. AMDL - Andrea M. Di Lellis SERENA Grounding scheme

  12. AMDL - Andrea M. Di Lellis DATA HANDLING: Main DPUs inheritance • FORMER AMDL’s related experiences: • CLUSTER CIS-2: DPU Designing & On-Board S/W (MAS281)‏ • DARA-NASA EQUATOR-S ESIC:On-Board S/W (MAS281) • DMARS-96 &ESA MARS EXPRESS PFS:FFT DPU Design & On-Board S/W (AD21000)‏ • DOUBLE STAR HIA: Composition Experiment OnBoard S/W (MAS281) • ESA SMART-1 AMIE: Microcamera - Power supply & S/C I/F board • NASA/JPL DAWN:VIR On board compression S/W & GSE • CURRENT AMDL’s related experiences: • ESA BEPICOLOMBO SERENA: PM and Design Manager • ESA EXOMARS IRAS: Electronics Design Manager

  13. AMDL - Andrea M. Di Lellis DHSU Developing SCU H/W demonstration mdel Full representativeSCU board 100% mastered

  14. AMDL - Andrea M. Di Lellis SERENA ELE/SCU CPPA

  15. AMDL - Andrea M. Di Lellis SCU SENSORS I/Fs: MIPA #1/2

  16. AMDL - Andrea M. Di Lellis SCU SENSORS I/Fs: MIPA #2/2

  17. AMDL - Andrea M. Di Lellis SCU SENSORS I/Fs: ELE-STROFIO #1/2

  18. AMDL - Andrea M. Di Lellis SCU SENSORS I/Fs: ELE-STROFIO #2/2

  19. AMDL - Andrea M. Di Lellis SENSORS I/F implementation: e.g.MIPA

  20. AMDL - Andrea M. Di Lellis SpW Testing Configuration SCU SIM: PENDER’s GR-XC3S-1500 FPGA based LEON3 PICAM & S/C SIM I/F & HOST USB I/F LVDS I/F

  21. AMDL - Andrea M. Di Lellis DHSU description The DHSU unit consists of the following functional blocks housed on a 100x160mm2 Eurocard board: - Hi Rel FPGA based Control Unit ( Leon3 FT)‏ -Hi Rel SRAM 512x2 kB EDAC Protected - HI Rel local power converter and power distribution switches - Rad Tolerant EEPROM 128x2 kB EDAC Protected Optionally on a second 100x100 mm2 mezzanine board: - Rad Tolerant 200 MIPS DSP Based DPU Compressor and glue logic Main DHSU tasks are: - To receive and to distribute command to Sub-sys - to acquire data from active Sub-Sys - to download science and H/K data through the S/C interface ; - to control and manages the IRAS suite functions - to control and distributes primary power to Sub-Sys

  22. AMDL - Andrea M. Di Lellis EDAC Faulty Case: corrupted bus: - Above: 1 err detected & recovered - Bottom: 2 err detected

  23. AMDL - Andrea M. Di Lellis DHSU: LEON 3 H/W STATUS: • Updating developing configuration of PENDER’s GR-XC3S-1500 FPGA based LEON3 development/prototyping board XCONFIG & XGRLIB and uploading procedures via IMPACT tool (Xilinx) tested and running for customized Leon3 configuration. For ACTEL developing procured A3PE3000 complete developing platform • Boot PROMs prepared. • Received directly from Gaisler a customized .MCS version which encloses the optional GR SpW core. S/W STATUS: • Updating S/W Development tools GRMON, GRSIM, BCC, GDB/DDD integrated on Cygwin and Win XP platforms. S/W development controlled under ECLIPSE 3.2. DOC Status • Preliminary definition of the internal I/Fs to Sub-Subsystem communication protocol issued. Provided a 2nd issue of Communication Interface Control Document BC-SRN-0045-00-01_.Doc OPEN ISSUES: • no major issues

  24. AMDL - Andrea M. Di Lellis BUDGETS Mass Power TM BUDGETS Ref BC-EST-RS-02522 Draft 2 TC Budget refined according to BC-SRN-0045-00-01 Communication Interface Control Document

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