Nanoionics -based RRAM Universal Memory

1. Nanoionics-based RRAMUniversal Memory Frank Rao Thai Tran Weijian Yang Wai Son (Wilson) Ko 5/11/2009 FTW2

7. Nanoionics-based RRAMUniversal Memory Frank Rao Thai Tran Weijian Yang Wai Son (Wilson) Ko 5/11/2009 FTW2

8. Outline • Memory market • Incumbents • Flash • DRAM • Memristive RRAM • Other competitors • Our Choice • Silicon-based nano-crossbar arrays • Conclusion

9. Our Need of Memory Data storage needs non-volatile Data buffering needs faster Flash Memory DRAM (Dynamic RAM) Nanoionic-based resistive RAM – Universal memory As fast as DRAM! As long data life time as Flash!

10. Moore’s Law of Memory [Source: Intel Corporation (2007)]

11. Constant Return from Memory Market Memory shares benefits from almost all the other hardware innovations Past: Future: PC Laptop Next generation wireless network Internet Cloud computing DC Wireless Netbook Portable Device Chip level bio-diagnostics

12. Volume of Target Memory Market [Source: SIA, November2008] 6.6B market share even we only replace NOR Flash!

13. Outline • Memory market • Incumbents • Flash • DRAM • Memristive RRAM • Other competitors • Our Choice • Silicon-based nano-crossbar arrays • Conclusion

14. Flash (RAM) • Non-volatile • Random access (only reading and writing) • Only segmental erasure of data slow writing speed • Building blocks are floating gate • transistors. • 1 Transistor for 1 bit http://en.wikipedia.org/wiki/Flash_memory

15. Flash (RAM) • Control gate controls current flow through • P-region + http://en.wikipedia.org/wiki/Flash_memory

16. Flash (RAM) • Control gate controls current flow through • P-region + e- e- http://en.wikipedia.org/wiki/Flash_memory

17. Flash (RAM) • Control gate controls current flow through • P-region + http://en.wikipedia.org/wiki/Flash_memory

18. Flash (RAM) • Control gate controls current flow through • P-region • Negative charge in float gate can “disable” • p-channel http://en.wikipedia.org/wiki/Flash_memory

19. Flash (RAM) • Control gate controls current flow through • P-region • Negative charge in float gate can “disable” • p-channel + http://en.wikipedia.org/wiki/Flash_memory

20. Flash (RAM) Reading Process: V>0 V>0 Neg. charges screen + + http://en.wikipedia.org/wiki/Flash_memory

21. Flash (RAM) Writing Process: V>0 GND + + Hot Carrier Injection - - - http://en.wikipedia.org/wiki/Flash_memory

22. Flash (RAM) Writing Process: V>0 V>0 - - Fowler-Nordheim Tunneling - - - http://en.wikipedia.org/wiki/Flash_memory NOTE: By design erasing is only possible in blocks in Flash devices

23. NOR and NAND Design NOR NAND http://en.wikipedia.org/wiki/Flash_memory • NAND-design allows higher densities, however NOR-design provides • faster reading. • NOTE: NAND-design uses tunneling for both writing and erasing

24. Dynamic RAM (DRAM) • Volatile • Fast (true random access ) • stored information should be • refreshed at least every 64ms • Power Consumption • 1 Transistor + 1 Capacitor for • every bit http://en.wikipedia.org/wiki/Dynamic_random_access_memory

25. Dynamic RAM (DRAM) • Volatile • Fast (true random access ) • stored information should be • refreshed at least every 64ms • Power Consumption • 1 Transistor + 1 Capacitor for • every bit

26. Holy Grail: Universal Memory which SatifiesMoores Law Memristive RRAM devices are promising candidates

27. Outline • Memory market • Incumbents • Flash • DRAM • Memristive RRAM • Other competitors • Our Choice • Silicon-based nano-crossbar arrays • Conclusion

28. Nanoionics-based Resistive Switching Memory Hysteresis Loop Waser and Aono, “Nanoionics-based resistive switching memories”, Nature Materials6, 833-840 (2007)

29. 0V +V -V Insulator Resistive Memories • Metal oxide • Insulator • Oxygen deficits • Dopants • Conduct current • Positive Voltage • Oxygen deficits migrates to fill the entire metal oxide • Resistance drops ↑Ω ↓Ω Bottom Electrode Top Electrode

30. 0V +V -V Insulator Resistive Memories • Positive Voltage • Oxygen deficits migrates to fill the entire metal oxide • Resistance drops • Negative Voltage • Oxygen deficits migrates to one side • Resistance increases ↑Ω ↓Ω Bottom Electrode Top Electrode

31. 0V +V -V Solid Electrolyte Memories • Ion conducting material • Resistor • Ions • Conduct current • Positive Voltage • Ions created at anode • Stopped by inert cathode • Ions buildup • Effective resistor gets smaller • Resistance drops Ion+ ↑Ω Inert Metal Cathode ↓Ω Electrochemically Active Anode

32. 0V +V -V Solid Electrolyte Memories • Positive Voltage • Ions created at anode • Stopped by inert cathode • Ions buildup • Effective resistor gets smaller • Resistance drops • Negative Voltage • Bridge dissolves • Resistance increases Ion+ ↑Ω Inert Metal Cathode ↓Ω Electrochemically Active Anode

33. Electron-ion Dynamics Hard to Model • Coupling of electron-ion dynamics was difficult to understand • No good mathematical model to predict behavior • Hindered development for many years • Memristor model predicts behavior well

34. 0V +V -V Memristor as a Model • Integrate to get • Memristance ↑Ω ↓Ω Bottom Electrode Top Electrode State variable Strukov, et al, “The missing memristor found”, Nature453, 80-83 (2008)

35. Memristor Model Predicts IV Curve Correctly • Hysteresis Loop is the signature of RRAM and memristor Strukov, et al, “The missing memristor found”, Nature453, 80-83 (2008)

36. Outline • Memory market • Incumbents • Flash • DRAM • Memristive RRAM • Other competitors • Our Choice • Silicon-based nano-crossbar arrays • Conclusion

37. Ferroelectric RAM Ferroelectric Domains Do the Trick for FRAMs Figure Courtesy: Linda Geppert, “The New Indelible Memories,” IEEE Spectrum, 49, March, 2003.

38. 100 150 50 200 0 Ferroelectric RAM Ferroelectric Domains Do the Trick for FRAMs E Figure Courtesy: Linda Geppert, “The New Indelible Memories,” IEEE Spectrum, 49, March, 2003.

39. 100 150 50 200 0 Ferroelectric RAM Ferroelectric Domains Do the Trick for FRAMs E Figure Courtesy: Linda Geppert, “The New Indelible Memories,” IEEE Spectrum, 49, March, 2003.

40. Ferroelectric RAM Ferroelectric Domains Do the Trick for FRAMs When scaling down, the signal becomes very weak! Figure Courtesy: Linda Geppert, “The New Indelible Memories,” IEEE Spectrum, 49, March, 2003.

41. Magnetic RAM MRAMs Do It With Tiny Magnets Figure Courtesy: Linda Geppert, “The New Indelible Memories,” IEEE Spectrum, 49, March, 2003.

42. Magnetic RAM MRAMs Do It With Tiny Magnets When scaling down, the current is so large that it may damage the wire. Figure Courtesy: Linda Geppert, “The New Indelible Memories,” IEEE Spectrum, 49, March, 2003.

43. Phase-change RAM PCRAMHeats Up, Then Cools Down Figure Courtesy: Linda Geppert, “The New Indelible Memories,” IEEE Spectrum, 49, March, 2003.

44. Comparison

45. Comparison Writing time (s) 1m NAND 100μ Volatile RAM 10μ NOR 1μ Flash 100n PRAM MRAM DRAM RRAM NV RAM FRAM 10n SRAM 1n 1M 10M 100M 1G 10G Memory Capacity (bit)

46. Outline • Memory market • Incumbents • Flash • DRAM • Memristive RRAM • Other competitors • Our Choice • Silicon-based nano-crossbar arrays • Conclusion

47. Very Potent Candidate: Crossbar Array based Si memristive System Ag P-Si a-Si S Hyun, KH Kim, W Lu, NanoLett. 9, No1, 2009 System: Ag/a-Si/p-Si

48. Very Potent Candidate: Crossbar Array based Si memristive System • Large scale (1kb) high-density crossbar array • Fabrication Yield over 98% • Write speed < 10 ns • Endurance > 105 cycles • Retention ~ 7 years (Extrapolation) • 50nm x 50nm (single device)→10Gb/cm2, • Claim that scalability < 30nm possible, Beware of Rs • CMOS compatible, Multi-Bit Capability already demonstrated S Hyun et al., NanoLett. 9, No1, 2009

49. Conclusion • RAM has a large market volume • Flash has scaling problem • DRAM is volatile and power-hungry • RRAM is the most promising candidate compared with other competitors to become the next generation memory. • Memristormodeling ease development • Silicon-based nano-crossbar arrays

50. Questions and Answers Thank you! F W2 T