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Medipix2 Parallel Readout System

Medipix2 Parallel Readout System. V. Fanti, R. Marzeddu, P. Randaccio. Dipartamento di Fisica e Sezione INFN Cagliari. 4-th IWORID Amsterdam 8 – 12 September 2002. Dynamic imaging with Medipix2. ONE CHIP 256x256x14 bits per frame 25 frames per second 2.3 x 10 7 bits per second

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Medipix2 Parallel Readout System

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  1. Medipix2 Parallel Readout System V. Fanti, R. Marzeddu, P. Randaccio Dipartamento di Fisica e Sezione INFN Cagliari 4-th IWORID Amsterdam 8 – 12 September 2002 IWORID 2002 - P.Randaccio

  2. Dynamic imaging with Medipix2 ONE CHIP • 256x256x14 bits per frame • 25 frames per second • 2.3 x 107 bits per second • 2.9 x 106 bytes per second EIGHT CHIPS • 1.8 x 108 bits per second • 2.3 x 107 bytes per second Serial I/O: 180 MHz Parallel I/O 32 bit: 5.7 MHz However, the readout speed should be as high as possible to reduce the dead time; aiming to 10% DT we should reach frequencies 10 times higher. IWORID 2002 - P.Randaccio

  3. The PC platform as acquisition system • Actually the PC is the best solution for: • Acquisition • Processing • Visualization • Storage • in imaging systems. IWORID 2002 - P.Randaccio

  4. PC architecture • North Bridge (Hi speed devices) South Bridge (Low speed devices) • I/O & interconnect busses: • Host Bus • Memory Bus • AGP (Graphics) • V-link (interbridge connection) • ATA (Hard disks) • PCI • USB • IEEE 1394 firewire • Legacy (ISA) …. obsolete IWORID 2002 - P.Randaccio

  5. Computer speed The typical processor clock frequency is 1 GHz The word length is 32 bits = 4 bytes but …. the data transfer rate is not 4 Gbyte/s ! • The speed is limited by the bus clock: • Host bus (between CPU and North Bridge): 200 MHz • Memory : 200 MHz AGP(4x) : 132 MHz • ATA : 100 MHz PCI : 33 MHz • ISA : 8 MHz IWORID 2002 - P.Randaccio

  6. Maximum transfer speed(the effective one) All values expressed in Mbytes/s IWORID 2002 - P.Randaccio

  7. The PCI bus : essentials Peripheral Component Interconnect (PCI) • 32-bit multiplexed data/address bus • Clock frequency : 33 MHz (66 MHz) • Maximum (theo) transfer rate : 132 MB/s (264 MB/s) • 3.3V & 5V operability • Plug and Play • single mode e burst mode transaction • reflected wave switching IWORID 2002 - P.Randaccio

  8. V V t < Tprop. t > Tprop. VTH VTH Incident wave Incident wave X X incident point bus end bus end Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 Slot 7 Slot 8 Slot 9 Slot 10 BUS Rterm Rterm Incident point Transmission lineStandard method: incident wave switching VME, ISA, EISA, …. busses IWORID 2002 - P.Randaccio

  9. Tprop<t <2 Tprop. V V t < Tprop. Reflected wave VTH VTH Incident wave X X incident point incident point bus end bus end Initiator Target Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 Slot 7 Slot 8 Slot 9 Slot 10 BUS Incident point PCI method: reflected wave switching IWORID 2002 - P.Randaccio

  10. Dev #1 Dev #n Dev #2 T_cyc T_high T_low Clock device #1 T_skew Clock device #2 PCI bus length limit d T_prop  10 ns ; d = bus length ; v = 2 ·108 m/s Worst case: x = 2d x = v ·T_prop = 2 m d  1 m (theo) Tprop = 30 ns – Tval – Tsu - Tskew IWORID 2002 - P.Randaccio

  11. Logic & I/O circuits Local bus (CMOS) BRIDGE PCI bus Bridge Connection between PCI bus and local bus for timing, operating voltage (5V/3.3V/2.2V), protocols IWORID 2002 - P.Randaccio

  12. PLX PCI9054 Bus Master I/OAccelerator IWORID 2002 - P.Randaccio

  13. Bridge PLX9054 • Bus Master interface • 32-bit data bus, 28-bit address bus • 3.3V, 5V tolerant • Local bus clock up to 50 MHz • Dual DMA channels • Six Read/Write FIFOs 16 Lword • Single and burst mode operation (block transfer up to 16 LWord) • Unlimited burst length • Memory spaces remap (up to 256 Mbytes of memory) IWORID 2002 - P.Randaccio

  14. Read D0 Read D1 Read D15 Read D2 = empty = full Burst read mode PCI Bus Local Bus Read FIFO (16 x 32 bit) PCI Read Request The bridge prefetches data from Local Bus device at max. clock speed Prefetched data is stored in the internal FIFO PCI bus reads data from the FIFO The PCI bridge returns data from internal FIFO in sequential address read operations until FIFO is empty IWORID 2002 - P.Randaccio

  15. I/O burst advantage Bus access (address, data, control cycles) slows down I/O operation. The prefetch with FIFOs reduces the time needed for bus access operations by a factor 16. CPU reads data directly from FIFO at very high speed. PCI Bus Local Bus PCI/Local bridge CPU North bridge FIFO FIFO Host memory South Bridge Host/PCI bridge IWORID 2002 - P.Randaccio

  16. Reading data from Medipix2 parallel port PCI bridge reads 16 Lword from Medipix2 parallel port through local bus CPU reads data from FIFO Acquisition rate is about 64 MByte/s 32 bits - 16 MHz mean acquisition rate IWORID 2002 - P.Randaccio

  17. Most PCs do not support burst read ! If the North Bridge has no FIFO (Intel bridges) the CPU readout phase is slower Acquisition rate is about 10 MByte/s IWORID 2002 - P.Randaccio

  18. Reading from a PCI device 4 G It is like a memory block transfer from PCI Address Space to program data. BIOS ROM PCI memory CPU From the software point of view it is just a move instruction. System RAM Each data transfer between bridges and busses is transparent to the software. 1 M IWORID 2002 - P.Randaccio

  19. Space0 Space1 Space2 Space3 Space4 Local bus I/O Address Space Configuration Address Space BRIDGE PCI Local Spaces A PCI device can be configured as five memory spaces with configurable address offset and range IWORID 2002 - P.Randaccio

  20. Memory space reserved for Medipix data Local Space 4 Not assigned Local Space 3 Not assigned Local Space 2 Not assigned Medipix matrix data read through parallel port Local Space 1 Serial data Local Space 0 Status Control IWORID 2002 - P.Randaccio

  21. MPRS: general schematic Medipix2 Testboard 127 I/O & Power Supply PCI Board Motherboard Flat cables 34-pin IWORID 2002 - P.Randaccio

  22. Motherboard Medipix Drivers 2.2 V Voltage Regulator Test Board LvdsCmos Z-adapter • Line drivers from Medipix to DAQ • CMOS - LVDS drivers • Power Supply, voltage regulator 3.3V – 2.2V 34-pin I/O flat cables IWORID 2002 - P.Randaccio

  23. IN Conn. OUT Conn. Z-adapter CMOS LVDS Voltage Reg. Medipix TB Connector DRIVERs Motherboard picture IWORID 2002 - P.Randaccio

  24. DAQ: PCI board Registers Buffers Address Decode Clock Bridge PCI 3.3 V EEPROM PCI Universal card for 32-bit, 33 MHz slot. Main components: • PCI Bridge: connection from PCI Bus to Local Bus • Registers for output lines • Buffers for input lines • Address decode circuit • Local Clock circuit • Voltage regulator 3.3V • Serial Eeprom IWORID 2002 - P.Randaccio

  25. PCI Board picture Input connector Output connector Address decode Output registers Input buffers Clock 3.3V reg. Eeprom Bridge IWORID 2002 - P.Randaccio

  26. PCI Board picture IWORID 2002 - P.Randaccio

  27. Software Hardware Control, acquisition & visualization (VBasic) Library Medipix.dll (C++) PCI board Motherboard Medipix2 Software IWORID 2002 - P.Randaccio

  28. Utility software: PCI board control panel • Scan PCI bus • Open device • Read/write test • Internal registers configuration IWORID 2002 - P.Randaccio

  29. Acquisition utilities • Set the DACs • Reset matrix data • Set pixel registers • Readout IWORID 2002 - P.Randaccio

  30. Image acquisition timing time Medipix2 Raw data memory Readout 2 ms MPRS Start ~ 0 ms MPRS Image reconstructionroutine X-rays Medipix photon counting phase ~38 ms Image Memory Stop ~ 0 ms MPRS Readout MPRS IWORID 2002 - P.Randaccio

  31. Image reconstruction Any image processing is made by software after the acquisition, in particular: • Image reconstruction with deserialization and derandomization The total time is : 256x8x14x32xTs = 917504xTs where Ts is the period of the inner software loop. The reconstruction time depends on CPU speed: however with a normal PC it lasts no more than 10 ms The software does the reconstruction during the Medipix2 photon counting phase, so it does not slow down the process. IWORID 2002 - P.Randaccio

  32. Conclusions • Parallel readout seems to be appropriate for the Medipix2 dynamic imaging acquisition. • Actual PCs are convenient platforms for the image acquisition, processing, storage and visualization. • Interfaces based on PCI bus are easy to develop and fast enough for our purposes. • The hardware complexity is transparent for the software thanks to the bridges. • Image reconstruction made by software simplifies MPRS hardware design. IWORID 2002 - P.Randaccio

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