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Chapter 1 Fundamentals of Computer Design

Chapter 1 Fundamentals of Computer Design. Review. Performance x = X is n times faster than Y. Increasing performance decreases execution time. Review. CPU Execution time = MIPS =. Amdahl’s Law.

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Chapter 1 Fundamentals of Computer Design

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  1. Chapter 1 Fundamentals of Computer Design

  2. Review • Performancex = • X is n times faster than Y Increasing performance decreases execution time. CSCE 614 Fall 2009

  3. Review • CPU Execution time = • MIPS = CSCE 614 Fall 2009

  4. Amdahl’s Law • The performance improvement to be gained from using some faster mode of execution is limited by the fraction of the time the faster mode can be used. • Speedup = CSCE 614 Fall 2009

  5. Amdahl’s Law • Fraction enhanced: the fraction of the computation time that can be enhanced. • Speedup enhanced: the improvement gained by the enhanced execution mode. CSCE 614 Fall 2009

  6. Example (Amdahl’s Law) • Suppose we want to enhance the processor used for Web serving. The new CPU is 10 times faster in Web serving. Assuming that the original CPU is busy with computation 40% of the time and is waiting for I/O 60% of the time, what is the overall speedup? CSCE 614 Fall 2009

  7. Example (Performance Eq.) • Suppose we have the followings: • Freq. of FP op (other than FPSQR): 25% • Avg. CPI of FP op: 4.0 • Avg. CPI of other instructions: 1.33 • Freq. of FPSQR: 2% • CPI of FPSQR: 20 Assume that the two design alternatives are to decrease the CPI of FPSQR to 2 or decrease the avg. CPI of all FP operations to 2.5. Compare these two design alternatives. CSCE 614 Fall 2009

  8. Instruction Set Architecture • The portion of the computer visible to the programmer or compiler writer. • RISC Architecture (MIPS, PowerPC, SPARC) • CISC Architecture (IBM 360/370, VAX) • Intel 80x86 • Internally uses RISC instruction set. • Externally supports an 80x86 instruction set. CSCE 614 Fall 2009

  9. RISC Architecture • Philosophy • Characteristics • Simple load-store architecture • Fixed format • Efficient pipelining CSCE 614 Fall 2009

  10. Pipelining Ease of Hardware Implementation Simple Instructions Simple Addressing Mode Fixed-Length Formats Large Number of Registers MIPS, … Simple Compilers Powerful Addressing Mode Powerful Instructions Efficient Instruction Encoding Few Registers VAX RISC vs. CISC CSCE 614 Fall 2009

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