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Electronics System of MC 2002.9 IHEP, Beijing ___________________________________________

Electronics System of MC 2002.9 IHEP, Beijing ___________________________________________ Muon Group, USTC, Hefei. CONTENTS Overview of structure Readout System of MC Test System of MC. Readout system. 3 Parts. Test subsystem. Two subsystems. Structure of MC Electronics system.

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Electronics System of MC 2002.9 IHEP, Beijing ___________________________________________

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  1. Electronics System of MC 2002.9 IHEP, Beijing ___________________________________________ Muon Group, USTC, Hefei

  2. CONTENTS Overview of structure Readout System of MC Test System of MC

  3. Readout system 3 Parts Test subsystem Two subsystems Structure of MC Electronics system Data, collected by FEC, transmitted to VME readout module by optic transmission module, and then saved into subevent buffer in VME readout mudule, to wait DAQ processing Turn back to contents of Talk

  4. CONTENTS Overview of structure Readout System of MC Test System of MC

  5. Structure of MC Electronics system FEC data chain

  6. Opt Trans DECL FEC 00 FEC 01 sys clk FEC 15 A Data Chain A FEC Structure • A data chain contains 16 FECs • A FEC has a 16-shift register in daisy chain • Connection between FECs is: output port of last shift register on a FEC is connected to input port of first shift register on next FEC

  7. Shift Reg of Next ch DISC FIFO Shift Regester Double Noise Rejection ch X Shift Reg of Last ch trigger FEC Structure DISC Circuit • Hit position information is transformed into data by DISC • Data of DISC are shaped and kept in 3.2s in Double Noise Rejection circuit to wait trigger • If trigger is coming data are stored in FIFO / if not data are renewed • 16 shift registers are connected as a 16-shift daisy chain

  8. DISC circuit • Discriminator circuit for input signal Turn back to FEC structure

  9. Shift Reg of Next ch DISC FIFO Shift Regester Double Noise Rejection ch X Shift Reg of Last ch trigger • Hit position information is transformed into data by DISC • Data of DISC are shaped and kept in 3.2s in Double Noise Rejection circuit to wait trigger • If trigger is coming data are stored in FIFO / if not data are renewed • 16 shift registers are connected as a 16-shift daisy chain FEC Structure DNR Notes

  10. Some notes of double noise rejection circuit Using monostable • Uesmonostable chip instead of FIFO to keep data in 3.2s in order to save cost of Muon readout system • Use noise rejection circuit to shape a pulse with 200 ns-width and 3.2s-delay to keep input Data of DISC and to reject noise, but System deadtime is a little big (3.3s) • Use double noise rejection circuit to reject noise and to reduce its deadtime, which just is 200 ns, it can be negligible • One shot (monostable?) comes from Aleph • Noise Rejection comes from Babar • Double Noise Rejection will be used in BESIII

  11. noise Strip X1 datum Strip X 3.2µs noise Strip X2 trigger t4 t1 t2 t3 Noise of using monostable • Data, corresponding to trigger at t4, is appeared at t2. So the correct data is 010 in the order of strip X1, X, X2 • But now we get wrong data – 111 because monostable at strip X1 is retriggered again at t3, and monostable at strip X2 is retriggered too at same time Noise rejection circuit • We can use un-retriggerable monostable to avoid noise at strip X1 • We can use noise rejection circuit to avoid noise at strip X2, because acceptance window is too wide

  12. LS221 Din Dout LS221 M1 3.3µs Strip X M2 3.1µs 200ns Dout Acceptance window Noise rejection circuit -- 1 • Noise rejection circuit • Waveform of Noise rejection circuit Next: principle of noise rejection • Shaped a pulse with 200 ns-width and 3.2s-delay • Make 3.3s deadtime to system using un-retriggering monostable chip 74LS 221

  13. M1 3.3µs Strip X1 M2 3.1µs 200ns Dout M1 3.3µs Strip X M2 3.1µs 200ns Dout M1 3.3µs M2 3.1µs 200ns Dout Trigger Acceptance window Noise rejection circuit -- 2 Next: Double Noise Rejection • Principle of noise rejection • Acceptance window and shaped pulse is narrow -- 200 ns-width • Reject noise of strip X1and strip X2 • Get correct data 010 • Deadtime to system is 3.3s Strip X2

  14. LS221 Bank 1 LS221 Dout Din LS123 Bank 2 LS123 Double noise rejection – 01 (structure) Next: Principle of Double Noise Rejection • There are two banks of noise rejection circuit • Bank 1 used an un-retriggering monostable chip • Bank 2 used a retriggering monostable chip • Reduce deadtime to 200 ns

  15. Double noise rejection – 02 (Principle of DNR) Turn back to FEC block diagram • Bank 1 can catch first pulse appearing during 3.2 s using un-retriggering monostable chip 74LS221 • Bank 2 can catch last pulse during 3.2 s using retriggering monostable chip 74LS123 • In fact more than 2 pulses can not be appeared during 3.2 s under data input rate 2 kHz (probability is 2x10-5) • Output pulse of “OR” gate is pulse of bank 1 or pulse of bank 2 • Pulse of bank 1 will be saved into FIFO if trigger corresponding to it coming/pulse of bank 2 will be saved if trigger corresponding to it coming; or both of them disappear if trigger is not coming • Deadtime contributed to system by this circuit can be negligible • Use counter chips to realize this circuit to avoid tolerance of extending Capacity and Resistance of monostable chips • In fact double rejection circuit is a pipeline device with two cells

  16. Shift Reg of Next ch DISC FIFO Shift Regester Double Noise Rejection ch X Shift Reg of Last ch trigger FEC Structure Depth of FIFO estimation • Data of DISC are shaped and kept in 3.2s in Double Noise Rejection circuit to wait trigger • Data are stored in FIFO as trigger is coming / data are renewed if trigger as trigger is not coming • 16 shift registers are connected as a 16-shift daisy chain

  17. Turn back to FEC block diagram Size and depth of FIFO • 1 bit for saving 1 Datum of a channel after available trigger • Set 6 banks (1 bit for a bank) in FIFO to avoid new event data lost if new trigger coming during time transmitting all the data from 256-shift daisy chain through fiber to chain event buffer in VME readout module • data lost is only 2.36 event data under 4kHz trigger rate for 8 hours of the running time by setting 6 banks • Contribution of FIFO to system deadtime can be negligible during time of data transmitting under this condition

  18. Shift Reg of Next ch DISC FIFO Shift Regester Double Noise Rejection ch X Shift Reg of Last ch trigger FEC Structure Shift register • Data of DISC are shaped and kept in 3.2s in Double Noise Rejection circuit to wait trigger • Data are stored in FIFO as trigger is coming / data are renewed if trigger as trigger is not coming • 16 shift registers are connected as a 16-shift daisy chain

  19. Chain data out DECL FEC15 FEC 00 Shift 15 Shift 00 Sysclk Shift register • In a FEC 16 shift registers get data in parallel • In a chain of data 16 FECs, connected in a daisy chain, contains 256 bits • 256 data go out at a port of data chain in series with differential ECL standard Turn back to MC electronics system

  20. FEC in Detector Ex-Box off Detector VME Crate in Contr Room Configure of MC Electronics system Extended box

  21. There are: • Optic transmission modules • A Test Function Generator module • A Threshold voltage Generator module Opt trans 2 Opt trans 1 Opt trans 3 Test Func Gen Test sig distr 1 Test sig distr 2 Thr vol Gen Thr vol distr 1 Thr vol distr 2 Sysclk distr 1 Sysclk distr 2 Trig sig distr 2 Power Supp 3 Trig sig distr 1 Power Supp 1 Power Supp 2 • Some distribution modules • Some power supply modules NIM modules in extended box Optic transmission

  22. TTL Contrl Contrl TTL chain00 DECL chain00 DECLchain01 TTL chain01 Trans Receiv Trans Drv Multiplexer (Decoder) Multiplexer (Encoder) Fiber TTL chain15 DECLchain15 Clk 20MHz Optic transmission 4096 data in 16 chains, loaded into the encoding chip in parallel Turn back to Elec. System reconstructed into its original parallel codes in decoding chip delivered to the receiver chip over a serial channel

  23. FEC in Detector Ex-Box off Detector VME Crate in Contr Room Configure of MC Electronics system VME Readout module

  24. Data SPPRS V M E B U S ACQ Chain Event Buffer 6×4 × 4-byte Sub- event Buffer 24×64 × 4-byte Ch 00 Series to parallel Test Test Switch Ch 01 Ch 15 • For Test: • Series data to parallel • Data saved into chain event buffer • Data into subevent buffer VME Readout Module Two work mode Format of data suppression • For data acquisition: • Data suppressions • Data saved into chain event buffer • Data into subevent buffer

  25. Suppress by FEC FEC Adds（10-bit） Undef（6-bit）FEC data（16-bit） CH.adds（4-bit） 0 Suppress Undef（2-bit） FEC Adds（10-bit） Format of data suppression Depth estimation of chain event buffer Use method of Suppressing by FEC in our design • as long as a datum of one channel on a FEC appears,data of whole 16 channels on a FEC as a 16-bit word will be stored • 10-bit code expresses the address of the 625 FECs • 16-bit code expresses the data of 16 channels, each channel occupying one bit • Number of compressed data for an event is 600 bytes if 100 hits/event • Store datum 1 and suppress datum 0 • 10-bit code expresses address of the 625 FECs • 4-bit code expresses address of channels of a FEC • Number of compressed data for an event is 1000 bytes if 100 hits/event

  26. Data SPPRS V M E B U S ACQ Chain Event Buffer 6×4 × 4-byte Sub- event Buffer 24×64 × 4-byte Ch 00 Series to parallel Test Test Switch Ch 01 • Set more banks to avoid the event data lost if the trigger signal comes again during the time of the transmitting event data from chain event buffer into subevent buffer • Will lose 1.97 event data under 4kHz trigger rate for 8 hours if 6 banks of the chain event buffer are set • This event data lost can be negligible Ch 15 Depth estimation of chain event buffer Depth estimation of subevent buffer

  27. Data SPPRS V M E B U S ACQ Chain Event Buffer 6×4 × 4-byte Sub- event Buffer 14×64 × 4-byte Ch 00 Series to parallel Test Test Switch Ch 01 • Set more banks to avoid the event data lost if the trigger signal comes again during the time of the DAQ processing • Will lose 1.24 event data under 4kHz trigger rate for 8 hours if 14 banks of the chain event buffer are set • This event data lost can be negligible Ch 15 Depth estimation of subevent buffer Turn back to contents of talk

  28. CONTENTS Overview of structure Readout System of MC Test System of MC

  29. Sig to FEC Func Gen Test cntr Test subsystem Test subsystem VME Test Control Module

  30. Command Buffer VME Bus interface Opt output Fiber VME test control module Turn back to Test Subsystem • ==== commands of test subsystem ==== • WRP – write pattern register to select pulse generation (yes/no) • WRC – write control register to adjust pulse width, amplitude and polarity • RDP – read pattern register to check command data • RDC – read control register to check command data

  31. Sig to FEC Func Gen Test cntr Test subsystem Test subsystem NIM Function Generator/Driver Distribution Module

  32. Command data input here to decide signal pattern and width, amplitude 48 Signals to match 40 data chains after driving NIM Function Generator/Driver Distribution Module Turn back to Test Subsystem

  33. Sig to FEC Func Gen Test cntr Test subsystem Test subsystem Driver on FEC

  34. Test Sig for a chain DISC 15 DISC 00 Sig Drv Sig Drv FEC 00 FEC 15 FEC 01 • Test whole 16 FECs in a data chain by one signal of one channel in Function Generator • Signal, drove again in a FEC, goes to 16 DISCs to test, then connected to next FEC in way similar to daisy chain • 48 output channels of Function Generator to match 40 data chains Sig Drv Test signal on a data chain of 16 FECs

  35. Structure of MC Electronics system The End

  36. Thanks a lot

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