EE 587 SoC Design & Test

1. EE 587SoC Design & Test Partha Pande School of EECS Washington State University pande@eecs.wsu.edu

2. Final Exam Review

3. System Level Design Issues • SoC Interconnection Architectures • Drawback of bus-based systems in terms of timing, power and other relevant parameters • Role of parallelism • Problem with long wires • Buffer Insertion • Problems with classical buffer insertion • How to deal with that • Multi-processor SoC (MP-SoC) platform design

4. Signal Integrity • Crosstalk Avoidance • Comparative study of different CAC schemes • How to cascade multiple CAC blocks for a wide bus so that there is no crosstalk between two sub blocks • Except coding what are the different methods of reducing coupling • Effect of inductance on buffer insertion • Effect of inductance on propagation delay • Electromigration • L di/dt noise • Decoupling capacitance • IR drop in power lines

5. Clock & Power Routing • How to control IR drop and L di/dt noise • What is the advantage of interleaved power & ground routing • Different ways of reducing power in clocking • Different clock routing mechanisms • Advantages Tapered H-tree • Configuration of gated clock

6. SoC Testing • What are the principal challenges in SoC testing • Design of scan flip-flop • How can you modify a pass transistor-based latch to make it scanable • JTAG instructions • LFSR pattern generation • Given a polynomial you need to derive the LFSR configuration • How you can modify a BILBO for different modes of operations

7. IDDQ Testing • What is bridging fault and how you can detect it • Applicability of IDDQ test in SoCs, what is the challenge? • How to switch off static current dissipating components for IDDQ testing. You need to explain with the help of proper circuit level design details • Relation between JTAG and IDDQ testing

8. Iddq Testing in SoC

9. Methods of Reducing Power • Architectural Decisions – has the highest impact (parallelism, pipelining, low activity designs, lower frequency operation ) • Circuit Techniques – gated clocks, low glitch circuits, reduce capacitances, reduce activity • Recent developments – Vdd scaling, VT adjustments • Software – low power instructions, algorithms • CAD tools to implement low-power techniques

10. Circuit Design Styles • Nonclocked Logic • CMOS, Pseudo-NMOS, Differential Cascade Voltage Switch (DCVS), Pass-Transistor • Clocked Logic • Domino, Differential Current Switch Logic (DCSL)

11. Circuit Design Styles • Advantages of DCSL gates • Principle of skewed CMOS • Dependence of short circuit current & leakage current on the skew ratio • Role of Vdd and Vt scaling • Principle of MTCMOS • Difference between logic and memory circuits in terms of Vdd and Vt scaling

12. MTCMOS • In active mode, low-VT MOSFET’s achieve high speed. • In standby mode when St'by signal is high, high-VT MOSFET’s in series to normal logic circuits cut off leakage current.

13. Issues in MTCMOS • Virtual ground not actual ground (lose some noise margin) • Can increase width of sleep transistor to reduce voltage at virtual ground but it will also increase subthreshold leakage and area of sleep transistor

14. Variable Threshold-CMOS • Threshold voltage of both devices are increased by adjusting the body-bias voltage in order to reduce subthreshold leakage current in standby mode • Requires twin-tub technology so that substrates of individual devices can be adjusted

15. Low Swing Interconnects • Dynamically Enabled Drivers • Low Swing Bus • Different level converter circuits

16. Dynamic Power Management • Dynamically reconfigures an electronic system to provide the requested services and performance levels with a minimum number of active components or a minimum load on such components • Selectively turns off or reduce the performance of idle or partially unexploited components

17. DPM Techniques • Predictive Technique • Static Technique • Adaptive Technique • Clock gating • Supply shut down

18. Low Power SRAM Design • Banked Organization • Divided Word Line • Pulsed Word line • Bit Line Isolation • Suppressing leakage in SRAM

19. Power & BIST • Modern design and package technologies make external testing increasingly difficult, and BIST has emerged as a promising solution to the VLSI testing problem • BIST is a DFT methodology aimed at detecting faulty components in a system by incorporating test logic on chip. • In BIST, an LFSR generates test pattern • LFSR-generated tests tend to take longer to reach acceptable levels of fault coverage, which increases the total energy consumption • Test vectors applied at nominal operating frequency will have a higher average power dissipation than normal mode. This is because in normal mode, successive functional input vectors applied to a given circuit have significant correlation; the consecutive vectors of an LFSR generated test sequence have a lower correlation.

20. Final Exam • 6-7 questions • Wire Engineering, SoC Design & Test, Low Power Design • These broad topics will be equally represented • Try to answer as much as you can • I will be testing you on whatever I have taught • Class Notes are very important