Design Issues of Flash-based SSD& Hybrid Disks

1. Design Issues of Flash-based SSD& Hybrid Disks Han-Lin Li Dept. Computer Science and Information Engineering National Taiwan University Advisor: Prof. Chia-Lin Yang

2. Trend of Flash Memory Application Sensor Node Cell Phone PDA Notebook Server Machine size Single Chip Solid State Drive Hybrid Disk Requirement Low Power Small Size Low Power Small Size Reliability Low Power Performance Reliability Small Size Low Power Performance Reliability

3. Outline • Background • NAND vs. NOR • Organization and characteristics of NAND flash memory • Trend of NAND flash memory technology • Design Issues of Flash-Based SSD • FTL design • Efficient garbage collection • Wear-leveling techniques • Multi-Chip (bank) flash memory • Flash memory as a swap device of virtual memory • Design Issues of Hybrid Disk • Our current work

4. NAND vs. NOR • NOR • Design for storing program code • Needs random-access for reading • Rarely needs to be updated • Cells are connected in parallel to the bit lines • Allowing cells to be read and programmed individually • NAND • Goal of NAND flash was to replace hard disks • Reduce chip area required to implement a given capacity • Reduce cost per bit • Increase maximum chip capacity • Cells are connected in series • Cells connected in series must be read in series • Occupy only a small fraction of the area of equivalent NOR cells

5. NAND vs. NOR

6. Organization of a Typical NAND Flash Memory NAND Flash Cell Single-level Cell (SLC) 1 bit/Cell Level 0 = Erased “1” Level 1 = Programmed to “0” Multi-level Cell (MLC) 2 bits/Cell Level 0 = Erased “11” Level 1 = Programmed to “10” Level 2 = Programmed to “01” Level 3 = Programmed to “00” Tunnel Oxide Control Gate Floating Gate Substrate Drain Source Stored electrons Erased = “1” Programmed = “0” 0 1 SLC Distribution Voltage 10 01 00 11 MLC Distribution Voltage

7. Organization of a Typical NAND Flash Memory NAND Flash Cell Potential problem Endurance Flash has limited write/erase times Data retention Stored electrons lost due to leakage Tunnel Oxide Control Gate Floating Gate Substrate Drain Source

8. Organization of a Typical NAND Flash Memory Samsung K9F1208R0B 1 Block = 32 pages 1 Page = 512B 1 Page Read/Write one page Block 0 Block 1 Erase one block Block 2 Block 3 … …

9. Flash Memory Characteristics Write once Written page can not be overwritten Flash block Flash Memory A free page

10. Flash Memory Characteristics Write once Written page can not be overwritten Flash Memory Live page Flash block A A live page A free page

11. Flash Memory Characteristics Write once Written page can not be overwritten Out-place update Flash Memory Dead page Flash block A’ A dead page New data A live page A free page

12. Garbage collection When # of free pages < GCt ( Garbage Collection Threshold ) Erase a block to reclaim dead pages Flash Memory Characteristics (cont’d) Flash Memory Flash block A dead page A live page A free page

13. Flash Memory Characteristics (cont’d) • Garbage collection • When # of free pages < GCt ( Garbage Collection Threshold ) • Erase a block to reclaim dead pages Flash Memory Flash block A dead page A live page A free page

14. Flash Memory Characteristics (cont’d) Garbage collection When # of free pages < GCt ( Garbage Collection Threshold ) Erase a block to reclaim dead pages Overheads Live data copying Block erase Flash Memory Flash block A dead page A live page A free page

15. Flash Storage System Architecture address translation table Physical address (bank, block, page) LBA 0 (0, 0, 3) … … 1 (0, 1, 2) 2 (1, 2, 1) Flash Memory Logic Block Address Garbage Collection File Translation Layer (FTL) Physical address MTD layer Command translation Physical device

16. As VLSI technology continues to scale, Advantage Capacity ↑ Disadvantage Data retention ↓ The floating gate is smaller # of electrons in floating gate ↓ The tunnel oxide is thinner Leakage current ↑ Endurance ↓ The tunnel oxide is thinner Write/Erase operations damage oxide more easily Trend of Flash Memory Technology Tunnel Oxide Control Gate Floating Gate Substrate Drain Source ITRS 2007 roadmap for memory technology.

17. Multi-Level Cell (MLC) flash Advantage Capacity ↑ Disadvantage Data retention ↓ Voltage gap between each state is smaller Trend of Flash Memory Technology Tunnel Oxide Control Gate Floating Gate Substrate Drain Source 0 0 1 1 SLC Distribution Distribution Time Voltage Voltage 10 01 00 10 01 00 11 11 MLC Distribution Distribution Time Voltage Voltage

18. Trend of Flash Memory Technology Page/Block size increasing [3] Latency ─ Throughput ↑ Operation 512B-page 2KB-page Read (page) 15 us 25us Write (page) 200 us 200 us Erase (block) 2 ms 2 ms Latency of operation in different flash page size [4,5]

19. Design Issues of Flash-Based SSD FTL design Reduce FTL’s memory requirement Efficient garbage collection Reduce garbage collection overhead Wear-leveling techniques Prevent blocks from being unevenly worn so as to lengthen the overall lifespan

20. FTL (File Translation Layer) • Map logical address to physical address to simulate traditional disk • FTL granularity • How many LBAs associated with an entry of FTL • FTL granularity ↑ • Smaller FTL table size • Larger update overhead Update page A Update page A FTL FTL Block X Block Y Block X Block Y A B A’ A B A’ A B A B B C D C D FTL granularity = 1 page FTL granularity = 2 page

21. Dynamic switch between fine-granularity and coarse-granularity in the FTL [7] Exploit the advantages of fine-grained FTL and coarse-grained FTL Switch to fine-grained FTL when out-place update triggered Reduce update overhead Switch to coarse-grained FTL when # of entries in fine-grained FTL exceeds limit Limit FTL table size LRU replacement policy FTL (File Translation Layer) (cont.) Update page A FTL Address Translation Table A Coarse-Grain Hash Table A Fine-Grain Hash Table Block X Block Y A B A’ A B C D

22. FTL (File Translation Layer) (cont’d) • Multi-level FTL [6] • Some LBAs are never used • Don’t create FTL entries for unused LBAs in Multi-level FTL • Save memory spaces

23. Efficient Garbage Collection • Objective • Reduce garbage collection overhead (# of live page copies) • Cost-benefit policy [16] • Choose the block of the largest score calculated by • age: the time past since last modification of the block • u: the live pages in the block • Hot-cold separation [10] • High # of write operation => hot data • Low # of write operation => cold data • Put hot data in the same block can reduce garbage collection overhead Block X Block X Block X Block X H H C C C C Hot data H H C C C C H Cold data After hot data are rewritten C C C C C H H Dead page C C C C H H

24. Wear-Leveling Techniques • Principle #1 • Allocate hot data to blocks with fewer erasure cycles • Principle #2 • At garbage collection, choose a block with fewer erasure cycles as the victim block

25. Hot-Cold Swapping [8] Periodically check If the difference between the erasure cycles of the oldest block and the youngest block > threshold Data stored in the oldest block and in the youngest block are swapped. Static-Dynamic [17] Static: Hot-cold swapping Dynamic: Blocks are allocated for new writes from a round-robin queue that sorts blocks in terms of their physical block addresses Wear-Leveling Techniques

26. Wear-Leveling Techniques • CAT [14] • When garbage collection, always erase the block of the minimal score calculated by formula μi: The space utilization of block i εi: The erasure cycle of block i. ai: age of block i.

27. References • Energy-Aware Flash Memory Management in Virtual Memory System,L.-H. Lin, C.-L. Yang, H.-W. Tseng, to appear in IEEE Transactions on Very Large Scale Integration (VLSI) Systems • Improving NAND Flash Based Disk Caches, T. Kgil, D. Roberts and T. Mudge, ISCA’ 08 • Future Outlook of NAND Flash Technology for 40nm Node and Beyond, K. Kim and J. Choi, NVSMW’ 06 • Samsung Electronics CO.,LTD. Datasheet of Samsung K9F1208R0B NAND flash, 2004. • Samsung Electronics CO.,LTD. Datasheet of Samsung K9K2G08X0A NAND flash, 2006. • A superblock-based flash translation layer for NAND flash memory, Kang, J., Jo, H., Kim, J., and Lee, J, EMSOFT '06 • An adaptive two-level management for the flash translation layer in embedded systems, C.-H. Wu, T.-W. Kuo, ICCAD’06 • Endurance Enhancement of Flash-Memory Storage Systems: An Efficient Static Wear Leveling Design, Chang, Y., Hsieh, J., and Kuo, T., DAC’ 07 • On Efficient Wear Leveling for Large-Scale Flash-Memory Storage Systems, L.-P. Chang, SAC’07 • An adaptive striping architecture for flash memory storage systems of embedded systems, L.-P. Chang and T.-W. Kuo, RTAS’ 02 • Energy-aware demand paging on NAND flash-based embedded storages, C. Park, J.-U. Kang, S.-Y. Park, and J.-S. Kim., ISLPED’ 04 • SWL: a search-while-load demand paging scheme with NAND flash memory, J. In, I. Shin, H. Kim, LCTES’ 07 • SmartSaver: turning flash drive into a disk energy saver for mobile computers, Chen, F., Jiang, S., and Zhang, X., ISLPED’ 06 • Using Data Clustering To Improve Cleaning Performance For Flash Memory, M. L. Chiang, Paul C. H. Lee, and R. C. Chang, Software - Practice and Experience, 1999. • An Effective Flash Memory Manager for Reliable Flash Memory Space Management, H. J. Kim and S. G. Lee, IEICE Transactions on Information and System, 2002. • A flash-memory based file system., A. Kawaguchi, S. Nishioka, and H. Motoda. , In Proceedings of the 1995 USENIX Technical Conference, pages 155–164, January 1995. • M-Systems, TrueFFS Wear-Leveling Mechanism“ • Wear Leveling in Single Level Cell NAND Flash Memories," STMicroelectronics Application Note (AN1822), 2006. • Samsung K8C1215EBM • Samsung K9F1G08R0A

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