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Overview

Overview. Last lecture Example: Ant in a maze More on Moore vs. Mealy Today Optimization of FSMs State assignment. Vending machine implementation. D1 = Q1 + D + Q0 N D0 = Q0’ N + Q0 N’ + Q1 N + Q1 D OPEN = Q1 Q0. CLK. Q0. D Q. Q'. REG out. N. Q1. D Q. Q'. REG out. D. OPEN.

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Overview

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  1. Overview • Last lecture • Example: Ant in a maze • More on Moore vs. Mealy • Today • Optimization of FSMs • State assignment CSE 370 – Winter 2002 - Sequential Logic-2 - 1

  2. Vending machine implementation D1 = Q1 + D + Q0 N D0 = Q0’ N + Q0 N’ + Q1 N + Q1 D OPEN = Q1 Q0 CSE 370 – Winter 2002 - Sequential Logic-2 - 2

  3. CLK Q0 D Q Q' REG out N Q1 D Q Q' REG out D OPEN D Q Q' COM out reset Map design to a (registered) PLD CSE 370 – Winter 2002 - Sequential Logic-2 - 3

  4. Retime design • OPEN is delayed by AND gate after Q1 and Q0 • Can remove this delay by retiming • Move output logic (AND gate) to eliminate delay • OPEN = Q1Q0 = (Q1+D+Q0N)(Q0'N+Q0N'+Q1N+Q1D) Original Design Retimed Design CSE 370 – Winter 2002 - Sequential Logic-2 - 4

  5. CLK Q0 D Q Q' REG out N Q1 D Q Q' REG out D OPEN D Q Q' REG out reset Retimed PLD implementation CSE 370 – Winter 2002 - Sequential Logic-2 - 5

  6. Synchronous (or registered) Mealy machine • Moore machine with no output decoding (like the retimed Moore vending machine) • Registered state and registered outputs • No glitches on outputs • No race conditions between communicating machines reg inputs outputs combinational logic for outputs and next state reg state feedback CSE 370 – Winter 2002 - Sequential Logic-2 - 6

  7. Finite state machine optimization • State minimization • fewer states require fewer state bits • fewer bits require fewer logic equations • Encodings: state, inputs, outputs (affects speed and size of FSM) • State code is a vector: log(n) to n bits (n  # of states) • trade flip-flop count for logic complexity • state encoding with fewer bits has fewer equations to implement • however, each may be more complex • state encoding with more bits (e.g., one-hot) has simpler equations • complexity directly related to complexity of state diagram • input/output encoding may or may not be under designer control CSE 370 – Winter 2002 - Sequential Logic-2 - 7

  8. Algorithmic approach to state minimization • Goal – identify and combine states that have equivalent behavior • Equivalent states: • same output • for all input combinations, states transition to same or equivalent states • Algorithm sketch • 1. place all states in one set • 2. initially partition set based on output behavior • 3. successively partition resulting subsets based on next state transitions • 4. repeat (3) until no further partitioning is required • states left in the same set are equivalent • polynomial time procedure CSE 370 – Winter 2002 - Sequential Logic-2 - 8

  9. Input Next State Output Sequence Present State X=0 X=1 X=0 X=1 Reset S0 S1 S2 0 0 0 S1 S3 S4 0 0 1 S2 S5 S6 0 0 00 S3 S0 S0 0 0 01 S4 S0 S0 1 0 10 S5 S0 S0 0 0 11 S6 S0 S0 1 0 S0 0/0 1/0 S1 S2 0/0 1/0 0/0 1/0 S3 S4 S5 S6 1/0 1/0 1/0 1/0 0/0 0/1 0/0 0/1 State minimization example • Sequence detector for 010 or 110 (e.g. input 010001110 yields output 001000001) Notice the short-hand notation for the transition table CSE 370 – Winter 2002 - Sequential Logic-2 - 9

  10. Input Next State Output Sequence Present State X=0 X=1 X=0 X=1 Reset S0 S1 S2 0 0 0 S1S3S40 0 1 S2S5S60 0 00 S3 S0 S0 0 0 01 S4 S0 S0 1 0 10 S5 S0 S0 0 0 11 S6 S0 S0 1 0 Method of successive partitions ( S0 S1 S2 S3 S4 S5 S6 ) ( S0 S1 S2 S3 S5 ) ( S4 S6 ) ( S0 S1 S1 ) ( S3 S5 ) ( S4 S6 ) ( S0 ) ( S3 S5 ) ( S1 S2 ) ( S4 S6 ) S4 is equivalent to S6 S3 is equivalent to S5 S1 is equivalent to S2 Polynomial time algorithm CSE 370 – Winter 2002 - Sequential Logic-2 - 10

  11. Input Next State Output Sequence Present State X=0 X=1 X=0 X=1 Reset S0 S1' S1' 0 0 0 + 1 S1' S3' S4' 0 0 X0 S3' S0 S0 0 0 X1 S4' S0 S0 1 0 S0 X/0 S1’ 0/0 1/0 S4’ S3’ X/0 0/1 1/0 Minimized FSM • State minimized sequence detector for 010 or 110 This method does not always yield the minimum number of states: easy to find counter examples CSE 370 – Winter 2002 - Sequential Logic-2 - 11

  12. 00 10 S0[1] S1 [0] 00 01 10 11 11 01 00 01 00 S2[1] S3 [0] 01 10 10 11 11 01 10 10 S4[1] S5 [0] 11 00 00 01 11 Example: Complex state diagram symbolic state-transition table inputs present next state output state 00 01 10 11 S0 S0 S1 S2 S3 1 S1 S0 S3 S1 S4 0 S2 S1 S3 S2 S4 1 S3 S1 S0 S4 S5 0 S4 S0 S1 S2 S5 1 S5 S1 S4 S0 S5 0 CSE 370 – Winter 2002 - Sequential Logic-2 - 12

  13. present next state output state 00 01 10 11 S0' S0' S1 S2 S3' 1 S1 S0' S3' S1 S3' 0 S2 S1 S3' S2 S0' 1 S3' S1 S0' S0' S3' 0 S1 S0-S1 S1-S3 S2 S2-S2 S3-S4 S0-S1 S3-S0 S3 S1-S4 minimized state table (S0==S4) (S3==S5) S4-S5 S0-S0 S1-S0 S1-S1 S3-S1 S4 S2-S2 S2-S2 S3-S5 S4-S5 S0-S1 S1-S1 S3-S4 S0-S4 S5 S1-S0 S4-S0 S4-S5 S5-S5 S0 S1 S2 S3 S4 Minimized FSM • Implication chart method (enumerates all possible combinations of states taken 2 at a time) (1) cross out incompatible states based on outputs (2) cross out more cells if indexed chart entries are already crossed out Polynomial time algorithm CSE 370 – Winter 2002 - Sequential Logic-2 - 13

  14. Minimizing incompletely specified FSMs • State equivalence is transitive for fully specified machines • But is not transitive if some states are “don't cares” e.g., state output S0 – 0 S1 is compatible with both S0 and S2 S1 1 – but S0 and S2 are incompatible S2 – 1 • No polynomial time algorithm for determining the state grouping that gives the smallest number of final states CSE 370 – Winter 2002 - Sequential Logic-2 - 14

  15. X Q1 Q0 Q1+ Q0+0 0 0 0 00 0 1 0 00 1 0 0 01 0 0 0 11 0 1 1 01 1 0 1 0– 1 1 0 0X Q1 Q0 Q1+ Q0+0 0 0 0 00 0 1 0 00 1 0 0 01 0 0 0 11 0 1 1 01 1 0 1 0– 1 1 0 0 X’ 00[0] X’ 01[1] X X’ 10 [0] X X Minimizing states may not yield best circuit • Example: edge detector - outputs 1 when last two input changes from 0 to 1 Q1+ = X (Q1 xor Q0) Q0+ = X Q1 Q0 CSE 370 – Winter 2002 - Sequential Logic-2 - 15

  16. X’ 00[0] X’ X X 10 [0] 01[1] X’ X’ 11[0] X X Another implementation of edge detector • "Ad hoc" solution - not minimal but cheap and fast CSE 370 – Winter 2002 - Sequential Logic-2 - 16

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