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C6xx. Architecture. TMS320 C6xx. Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004. On Chip Ex. Memory. Off Chip Ex. Memory. Internal Buses. P E R I P H E R A L S. .D1. .D2. .M1. .M2. Regs (A0-A15). Regs (B0-B15). .L1. .L2. .S1. .S2. Control Regs . CPU.
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C6xx Architecture TMS320C6xx Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
On ChipEx. Memory Off Chip Ex. Memory Internal Buses PERIPHERALS .D1 .D2 .M1 .M2 Regs (A0-A15) Regs (B0-B15) .L1 .L2 .S1 .S2 Control Regs CPU 'C6x - System Block Diagram Harvard PC
256 32/64 32/64 32/64 32/64 32/64 'C6x - System Block Diagram Mappate in memoria I/O 32 Mappate in memoria
'C6x - Peripherals On Chip Each of these peripherals has a module dedicated to them and each of these can exist on the C6x Off Chip
clk1 clk2 clk3 Ad1 Ad2 Ad3 clk0 EMIF
Memory Sizeper device HARVARD Off Chip Memory Fast Slow
McBSP/ASP and Utopia Bus I2C: Protocollo Seriale Sincrono (due linee bidirezionali, clock e dati sincroni, più la massa) ATM:Asynchronous Transfer Mode
GPIO • LED • SWITCH
x8 Clock Cycle
Fast Slow C6416-DSK Architecture