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ITRS Roadmap Design + System Drivers 2006-7 Worldwide Design TWG

ITRS Roadmap Design + System Drivers 2006-7 Worldwide Design TWG. What’s New in 2005 Design & System Drivers. First Design For Manufacturability roadmap DFM roadmap tool Interface with other groups. First worldwide quantitative design technology roadmap System-level Logic/circuit/layout

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ITRS Roadmap Design + System Drivers 2006-7 Worldwide Design TWG

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  1. ITRS Roadmap Design + System Drivers2006-7 Worldwide Design TWG

  2. What’s New in 2005 Design & System Drivers • First Design For Manufacturability roadmap DFM roadmap tool Interface with other groups • First worldwide quantitative design technology roadmap System-level Logic/circuit/layout Verification DFT DFM • New SoC model captures emerging market driver Consumer driver improves alignment with other roadmaps • Emerging SoC fabric drivers updated Analog & MIxed-signal Embedded memory In next 10 years, new drivers and technology limitations will require design technology overhaul at all abstraction levels

  3. Design “Versus” System Drivers

  4. Design Chapter

  5. Design: Content organization • Promotion of key design challenges • Small subset of them as top-level ORTC table General Selection Productivity Power DFM Interference Reliability Mapping System design Logic/circuit Physical D Design verification Design Test DFM (new)

  6. New:Overall Design Technology Challenges

  7. New:Overall Design Technology Challenges

  8. Design Technology Cycle (Pre-Production) ~10-year cycle

  9. System-Level Requirements Source: Wolfgang Rosenstiel’s Team

  10. Logic/Circuit/Physical Solutions

  11. DFT Solutions Table

  12. DFM  Variability Framework Actual (bottom-up) / required (top-down) variability Performance (delay) Power (energy) “Gate” delay (power) “Wire” delay (power) Intermediate parameters Intermediate parameters (Vdd, T) Rsheet Vt Leff tOX NA Weff L t W tILD Other TWGs (PIDS, Interconnect, etc.)

  13. Roadmapping DFM Issues inc. Variability • Current recommendation • Not to extend 10% CD control beyond 15% • Below 15% still unclear  12% possibly acceptable

  14. System Drivers Chapter

  15. ITRS System Drivers Market and Application Alignment • ITRS Design Group focuses on roadmapping • Design Technology challenges and solutions • Drivers for Silicon Systems design • ITRS partially aligned by market/application driver “Fabric” drivers: CPU, DSP/SPU, memory, AMS “Market” drivers: consumer mobile, office • Full alignment will be accomplished in ITRS 2006-7

  16. ITRS-iNEMI Domain Space iNEMI (emulators) Market requirements ITRS (Drivers) Tech requirements Chip level System level

  17. Consumer Portable System Driver(Japan Design TWG) ES Level Methodology Very large block reuse Intelligent testbench Large block reuse Small block reuse Tall thin engineer IC implem. tools In-house P&R General $10,000 $1,000 Selection Productivity Power Manufac. Interference Reliability $100 Design cost ($M) $10 $1 Design process System design Logic/circuit Physical D Design verification Design Test DFM (new) 1990 1996 2000 2002 2004 2010 1992 1994 1998 2006 2008 Mobile /Consumer SoC PE-1 PE-2 … PE-n Main Prc. Memory Updated productivity table  cost Peripherals Preserve consistency

  18. Key Driver Trends • Power consumption a first-class constraint Both for portable and non-portable applications • Highly parallel architectures Increasing number of “small” processing unit • System-On-Chip design techniques Assemble lots of pre-designed blocks

  19. --- Overall Requirements (cont.) SOC Requirements

  20. Office (MPU) Driver

  21. Memory Driver

  22. 4. System Drivers “Matrix” Alignment Fabrics HP CP MPU 2005 PE(DSP) Size/weight ratio, battery life… Power, interconnect speed… Memory AMS Medical Automotive Office Network Defense Portable [Industrial] Markets

  23. 4. System Drivers “Matrix” Alignment Fabrics MPU 2006 PE(DSP) Memory AMS Medical Automotive Office Network Defense Portable [Industrial] Markets

  24. 4. System Drivers “Matrix” Alignment Fabrics MPU 2007 PE(DSP) Memory AMS Medical Automotive Office Network Defense Portable [Industrial] Markets

  25. Systems Driver Chapter Future Structure

  26. Summary  2005 Design & System Drivers • First Design For Manufacturability roadmap DFM roadmap tool Interface with other groups • First worldwide quantitative design technology roadmap System-level Logic/circuit/layout Verification DFT DFM • New SoC model captures emerging market driver Consumer driver improves alignment with other roadmaps • Emerging SoC fabric drivers updated Analog & MIxed-signal Embedded memory In next 10 years, new drivers and technology limitations will require design technology overhaul at all abstraction levels

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