Reliability of Programmable Input/Output Pins in the Presence of Configuration Upsets

1. Reliability of Programmable Input/Output Pins in the Presence of Configuration Upsets Nathan Rollins1, Michael J. Wirthlin1, Michael Caffrey2 and Paul Graham2 1 2 Department of Electrical and Computer Engineering Brigham Young University Provo, UT Los Alamos National Laboratory Los Alamos, NM This work was supported by Los Alamos National Laboratory, U.S. Department of Energy (LA-UR #02-5363)

2. Benefits of SRAM FPGAs in Space • FPGAs Can Be customized To Application-Specific Algorithms • Customizable datapath for application specific computations • Often faster and more efficient than a programmable processor • FPGAs Are Reprogrammable • Configuration after the spacecraft has been launched • FPGA resources can be used for multiple instruments, missions, or changing spacecraft objectives • Errors in an FPGA design can be repaired while in orbit

3. Los Alamos Cibola Flight Experiment • Reconfigurable RF payload • Uses 9 Virtex V1000 FPGAs • Target 2.4 Gbit/sec continuous processing • 2 12-bit 100 MHz ADC • Wide-band RF processing

4. Challenges of SRAM-Based FPGAs in Space • Static memory sensitive to single-event upsets (SEU) • Large amount of static memory in FPGAs • Configuration memory • User memory and flip-flops • Upsets within the configuration memory may modify the behavior of the design • Internal Logic and Interconnect • Global clocking and configuration modes • Operation of Input/Output pads • Goal: Study the effects of configuration upsets on Input/Output Blocks

5. Radiation exposure upsets IOB configuration Input/Output Block Risk FPGA System Device IOB Pad

6. IOB Reconfigured as an Output Input/Output Block Risk FPGA System Device IOB Pad

7. Input/Output Block Risk FPGA System Device IOB Pad Drive conflict on System bus

8. Virtex Input/Output Block Architecture T 1 0 B B O PAD B I IQ

9. Virtex Input/Output Block Architecture • Multiple Operating Modes (Input, Output, Bidirectional) • Internal Flip-Flops (Input, Output, and Tri-State Control) • Logic Standards (LVTTL, LVCMOS, PCI, LVDS, GTL, HSTL, etc.) • Programmable Drive Strength (2-24 mA) • Programmable Slew Rate and Termination • 324 Configuration Bits per IOB • How sensitive is the IOB to upsets within the configuration memory?

10. IOB Configured as an Input T 1 0 B B 1 O PAD B I IQ

11. IOB Configured as an Output T 1 0 B B 0 O PAD B I IQ

12. Configuration Upset Test Methodology • Artificially modify configuration bitstream to simulate radiation-induced upsets • Modify FPGA configuration bitstream (single-bit or multiple-bit • Configure FPGA with modified • Repair configuration bitstream and reconfigure • Probe operation of circuit to identify results of configuration faults • Previous tests have tested user logic and routing

13. FPGA Pad Reader FPGA Under Test High logic level readable from host IPAD OPAD IPAD 1 Pullup (~13 k) pulls signal to a high logic level IOB Configuration Sensitivity Test

14. FPGA Pad Reader FPGA Under Test Low logic level read by host IPAD OPAD IPAD 0 IOB configured to drive pad and overcomes pullup IOB Configuration Sensitivity Test

15. IOB Configuration Sensitivity Test FPGA Pad Reader FPGA Under Test IPAD OPAD IPAD IPAD OPAD IPAD Two IOBs tested simultaneously to catch both stuck-at-0 and stuck-at-1 IOB faults

16. Single-bit Upset Results • All 324 IOB configuration bits toggled individually • Only one single-bit configuration upset detected • Addition of a pull-up on the stuck-at-1 test • Addition of pull-down on stuck-at-0 test is not detectable (the pull-up is stronger than the pull-down) • This single-bit upset is not a significant problem

17. IPAD OPAD IPAD IPAD OPAD IPAD Single-bit Upset Results • All 324 IOB configuration bits toggled individually • Only one single-bit configuration upset detected

18. Multi-bit Upset Results • All two-bit combinations of the 324 IOB configuration bits toggled (104652 configuration bit pairs) • Single-bit upset failure ignored • 2 two-bit combinations cause a serious error • Stuck-at-0 with strong drive • 1024 serious two-bit failures for 512 IOBs • 3.56 x 1013 pairs in entire bitstream • Probability of any two-bit failure causing a serious IOB error = 2.9 x 10-11

19. Multi-bit Upset Results IPAD OPAD IPAD OPAD IPAD Will cause strong contention with opposing output driver

20. IOB Configuration Upset Detection • Detection of upset extremely important • IOB failure will result in excessive current • IOB must be repaired through full reconfiguration as soon as possible • IOB Configuration Failure Detection Approaches • Redundant IOBs • Configuration scrubbing

21. IOB Failure Detection Using Configuration Scrubbing • Use additional IOBs to detect logic differences • Error detected quickly • Very expensive use of FPGA resources System Device External Drivers FPGA IPAD error

22. IOB Failure Detection Using Readback • Contents of configuration bitstream can be obtained by performing a “Readback” operation • Readback configuration bitstream • Compare readback bitstream with original configuration • Failure detected when bitstream discrepancies are found • Relatively slow • Requires additional system resources • Micro-processor and memory • Configuration controller

23. Conclusions • Virtex IOB architecture tested for susceptibility to configuration upsets • No single-bit configuration upsets will create a high-strength output driver • Two double-bit configuration upsets will create a high-strength output driver • Very low probability of failure • IOB failure detection can be used to detect unwanted high-strength drivers