Prepared by: Nedal Altaradeh 20093024012 Directed by: Dr.Abd Alra’ouf Alrjoub Date:

1. Prepared by: Nedal Altaradeh 20093024012 Directed by: Dr.Abd Alra’ouf Alrjoub Date: 3/5/2012 “A Novel Approach For CMOS Inverter in Sub-100 Nanoscale ” Prepared by: Eng.Nedal Al-Taradeh Supervised By: Dr.Mamoun Al-Mistarihi & Dr.AbdoulRjoub March,2013

2. Introduction: (Motivations)

3. OUTLINE MOSFETOperations Introduction to Transistor CMOS Inverter Problemstatement Sub threshold leakage Leakage current Models in Nanoscale Gate leakage Band to Band leakage Modeling the Overshooting in CMOS inverter Modeling Nano Prameters Modeling of Mobility Conclusion and Future Work Simulation &Results

5. Logic Operation Modes of Transistor

6. Logic Operation Modes of Transistor

7. CMOS Inverter

8. MOSFET modeling

9. CMOS Inverter

10. MOSFET modeling • Modeling can be defined as: • “The method of finding the parameter values for equations by writing a set of fixed model equations that link voltages and currents • Basic MOS model components: 1. Equations describing Ids (Vds) and Ids (Vgs) 2. Parameters that link the technology being used for fabrication.

11. MOSFET modeling • Modeling can be defined as: • “The method of finding the parameter values for equations by writing a set of fixed model equations that link voltages and currents • Basic MOS model components: 1. Equations describing Ids (Vds) and Ids (Vgs) 2. Parameters that link the technology being used for fabrication.

12. Leakage current in Nanoscale CMOS • Leakage current is: • The unwanted current flows through the Cut-off (Stand by) mode of operation for MOSFET . • Reasons for Leakage current flowing: • Reverse biasing of transistor. • Aggressive scaling down of transistor(SCE).

13. Types of Leakage current.

14. Sub-threshold current (Isub) • Caused by the reverse biasing voltage of the transistor at standby mode. • It depend on some factors: • Weak inversion current(IWI). • Drain induced barrier lowering(DIBL). • Body effect(m). • Gate induced drain Lowering (GIDL).

15. Sub-threshold current (Isub) • Weak inversion current(IWI). • Due to minority carrier concentration . • Little variation of electrostatic potential causes little field variation. • Subthreshold conduction dominated by diffusion current. • Carriers moves along the surface of channel by diffusion with the same method of electrons.

16. Sub-threshold current (Isub) • Weak inversion current(IWI) expresses as: • Where: m is the body effect coefficient and also it is called (sub threshold swing coefficient) and it equal: • (2) • : is the maximum depletion layer width, • is the gate oxide thickness, • is the capacitance of the depletion layer, • is the oxide capacitance, : is the low field mobility,are the permittivity of silicon and oxide respectively. 1)

17. Sub-threshold current (Isub) • Drain Induced Barrier Lowering: • The electrostatic potential reduces by the increasing of the drain voltage. • Overlapping layer region of the drain and source. • Threshold voltage, and sub threshold current are also affected by the variation of the drain voltage. • we can reduce it by efficient channel doping, and higher barriers.

18. Sub-threshold current (Isub) • Drain Induced Barrier Lowering Calculation :

19. Sub-threshold current (Isub) • The final expression of the DIBL component in Nanoscale devices can be described as in the following equation: Now before Where: is the DIBL, Vdsl, Vdsh are the higher and lower drain voltage. Where: the width of depletion layer. junction depth for Drain and Source. (3)

20. Sub-threshold current (Isub) • Observations: • Value of DIBL depends on the drain voltage and the threshold voltage difference • Threshold voltage depends on: • The depth of Source /Drain junction. • Substrate doping concentration. • Depletion layer width. • Trans conductance. • Oxide thickness. • Oxide capacitance. • Electron Charge. • Body effect.

21. Sub-threshold current (Isub) • Gate Induced Drain Lowering(GIDL): • Occurs as a reason of Oxide thickness reduction. • Higher electrostatic potential at oxide insulator allows the electrons to tunnel to other parts of transistor. • Another delay also added to the subthreshold leakage. (5) • (6)

22. Sub-threshold current (Isub).Cont… • The body effect ( ): • The threshold voltage increased with increasing of reverse biasing. • The variation of threshold voltage due to SCE is called body effect. • It can be modeled in Nanoscale as:

23. Sub-threshold current (Isub).Cont… • The total current equation is modeled as: • Where: is the GIDL component. • is the DIBL component. • is the body effect linearization coefficient.

24. The BTBT Current.(IBTBT) • The Band to Band Tunneling): • Occurs because of reverse biasing. • Higher electric field allows the electrons to tunnels through PN junction bet. (Drain and Substrate). • When the junction voltage>band gap voltage. • The tunneling of electrons is occurred through the valence gap of n side substrate .

25. The BTBT Current.(IBTBT) • The Band to Band Tunneling): • The current density cab describe as: • is the gap energy. Is reduced blanch constant. • is the effective free electron mass.

26. The BTBT Current.(IBTBT) • The Band to Band Tunneling): • The total BTBT current contains two component: • The source BTBT current • The Drain BTBT current. • Its can describe as: Where : x,y are the coordinate of any point at PN junction.

27. The BTBT Current.(IBTBT) • Rectangular approximation): • The integration cannot be solved at values Rectangular approximation is used:

28. The BTBT Current.(IBTBT) • The current will be:

29. The BTBT Current.(IBTBT) • Some correction parameters are added to model the fluctuation of gate field and applied voltage: Where:

30. The Gate leakage • Occurred as result of reducing Oxide thickness. • The higher electric field allowing electrons tunneling through forbidden energy gap. • It has five components: • The parasitic gate leakage from gate to S/D over lap region (Igo) and which creates two currents (Igso) and (Igdo), • The gate to the inverted channel leakage (Igc) which have two parts (Igcs) and(Igcd), • The gate to substrate leakage current (Igb).

31. The parasitic gate leakage from gate to S/D over lap region (Igo) • The dominant type of leakage. • Caused by the overlapping between gate and drain/source region through oxide. • It can be described as: .

32. gate leakage from gate to S/D over lap region (Igo)(new work) • Image charge at the interface between the Si and SiO2 on the oxide region make reduction at oxide height: • The oxide field also can be describe as: .

33. The parasitic gate leakage from gate to S/D over lap region (Igo) • The dominant type of GATE leakage. • Caused by the overlapping between gate and drain/source region through oxide. • It can be described as: .

34. gate leakage from gate to S/D over lap region (Igo)(new work) Old equation: . (25)

35. The Gate to inversion leakage • The gate to inversion layer current with source and drain component can be described as: • Where: • The only type of leakage that depends at Vgs.

36. Modeling The Overshooting of Nanoscale CMOS The MOSFET output using Sakurai low equal to: Linear Region: Saturation Region: Where: We Found K,,and B by extraction

37. Modeling The Overshooting of Nanoscale CMOS (Regarding Leakage Effect)

38. Modeling The Overshooting of Nanoscale CMOS

39. Modeling The Overshooting of Nanoscale CMOS The overshooting occurs when P-Type is in linear region and N-Type in Cut off. The CMOS output Differential equation using KCL is: (32) (33) ,

40. Modeling The Overshooting of Nanoscale CMOS Supoose that :

41. Modeling The Overshooting of Nanoscale CMOS • After calculating A , B, and C: • The final expression will be: • After integrating Eq.(35) we have Vout(t) equal to: • Vout(t) =1.81×1031t 3-3.2×1020t 2+1.86×109t+0.9 (36)

42. Modeling The Overshooting of Nanoscale CMOS (Neglecting Leakage Effect)

43. SIMULATION PART • This part contains our results of: • The DIBL Model simulation • The sub threshold current Simulation. • The gate current simulation • The band to band current simulation. • The CMOS Overshooting Model with leakage • The CMOS Overshooting Model without leakage

44. Simulation conditions

45. Simulation Tool

46. The DIBL VS vds.

47. The DIBL VS substrate doping.

48. The DIBL VS substrate doping.

49. Isub VS gate Voltage.

50. Isubfor recent &proposed.