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S. Reda EN160 SP 07

S. Reda EN160 SP'07. Array subsystems. SRAMDRAMROM. S. Reda EN160 SP'07. Array architecture. . . . . . . . . . . . Word 0. Word 1. Word 2. Word. N. -. 2. Word. N. -. 1. Storage. cell. 2m. bits. N. words. . . . . . . . . . . . . . . . . . . . . . . . . . . S. 0. S. 1. S. 2. S. N. -. 2. S. N. -.

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S. Reda EN160 SP 07

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    1. S. Reda EN160 SP’07

    2. S. Reda EN160 SP’07 Array subsystems SRAM DRAM ROM

    3. S. Reda EN160 SP’07 Array architecture

    4. S. Reda EN160 SP’07 Array architecture

    5. S. Reda EN160 SP’07 1. Core. 12T SRAM Cell Basic building block: SRAM Cell Holds one bit of information, like a latch Must be read and written 12-transistor (12T) SRAM cell Use a simple latch connected to bitline 46 x 75 ? unit cell

    6. S. Reda EN160 SP’07 6T SRAM Cell Cell size accounts for most of array size Reduce cell size at expense of complexity 6T SRAM Cell Used in most commercial chips Data stored in cross-coupled inverters Read: Precharge bit, bit_b Raise wordline Write: Drive data onto bit, bit_b Raise wordline

    7. S. Reda EN160 SP’07 SRAM Read Precharge both bitlines high Then turn on wordline One of the two bitlines will be pulled down by the cell Ex: A = 0, A_b = 1 bit discharges, bit_b stays high But A bumps up slightly Read stability A must not flip

    8. S. Reda EN160 SP’07 Reading within the context of a column

    9. S. Reda EN160 SP’07 SRAM Write Drive one bitline high, the other low Then turn on wordline Bitlines overpower cell with new value Ex: A = 0, A_b = 1, bit = 1, bit_b = 0 Force A_b low, then A rises high Writability Must overpower feedback inverter

    10. S. Reda EN160 SP’07 SRAM Column Example

    11. S. Reda EN160 SP’07 2. Decoders n:2n decoder consists of 2n n-input AND gates One needed for each row of memory Build AND from NAND or NOR gates Static CMOS

    12. S. Reda EN160 SP’07 Large decoders For n > 4, NAND gates become slow Break large gates into multiple smaller gates

    13. S. Reda EN160 SP’07 Predecoding Many of these gates are redundant Factor out common gates into predecoder Saves area Same path effort

    14. S. Reda EN160 SP’07 3. Column circuitry Some circuitry is required for each column Bitline conditioning Sense amplifiers Column multiplexing

    15. S. Reda EN160 SP’07 Bit preconditioning and sense amplifiers Precharge bitlines high before reads

    16. S. Reda EN160 SP’07 Column multiplexing Recall that array may be folded for good aspect ratio Ex: 2 kword x 16 folded into 256 rows x 128 columns Must select 16 output bits from the 128 columns Requires 16 8:1 column multiplexers

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