East-West Design & Test Symposium 2009

1. East-West Design and Test Symposium System in Package. Diagnosis and Embedded Repair East-West Design & Test Symposium 2009 Moscow, Russia, September 18-21, 2009 Authors : Hahanov V.I. Litvinova E.I. Sushanov A.V. Galagan S.S. Scientific adviser : Vladimir Hahanov Kharkiv National University of Radioelectronics (Ukraine)

2. CADSM 2009 Polyana Algebra-Logical Method for System-in-Package Diagnosis 1 Presenter: Aleksey Sushanov

3. East-West Design and Test Symposium Agenda System in Package Advantages System in Package Problems Purpose and Tasks I-IP Infrastructure Algebra-logical Method of the Fault Diagnosis Model of Diagnosis Process The Program Module Algebra-logical method for FPGA components repair Example of FPGA repair The program module Conclusions

4. East-West Design and Test Symposium System in Package Advantages Increase digital systems productivity Volume miniaturization Product weight reduction Reduction of signals distribution delays Power consumption and device costs

5. East-West Design and Test Symposium System in Package Problems Hardware complication Design and manufacturing cost Absence of die quality assurance SiP Low Assembly Yields Complex Repair Process Complexity of heat removal management Wafer/Die/Substrate Test Functional module test

6. East-West Design and Test Symposium Purpose and Problems The research purpose is: improvement of digital system quality through methods development for functional modules diagnosis and repair based onusing reserve chip area Problems to solve are: Working out of methodforlogicblocks matrix detour for defective components covering Adaptation of algebra-logical method for embedded diagnosis Working out of digital crystal logic blocks matrix model in the form of functional cells Practical results of research

7. East-West Design and Test Symposium I-IP Infrastructure 1 The infrastructure includes following I-IP-modules: • 1) Observation for state of input and output lines in functioning; • 2) Testing of functional modules by means of input of the fault detection patterns from different test generators; • 3) Fault diagnosis by means of analysis of information obtained on the testing stage; 4) Repair of functional modules and memory after fixation of negative testing result; 5) Measurement of the general characteristics and parameters of device; 6) Reliability and fault tolerance of a device operation in working. Integration F-IP and I-IP on one chip will allow to provide industrial and operational SoC reliability, thus it should be imperceptible for standard SoC functionality.

8. East-West Design and Test Symposium I-IP Infrastructure 2 I-IP for Multi-Time Repair Integration F-IP and I-IP modules allows to exclude the external equipment for restoration, reduces industrial expenses, increases efficiency of restoration, and also increases productivity and efficiency of chip area use.

9. East-West Design and Test Symposium Algebra-logical Method of the Fault Diagnosis Boundary scan technology Register stage using Cell quantity = problem lines Test vectors arrive into model and real device Model reaction Device reaction Scoreboard analyzes diagnosis result Result – set of fault on test current pattern

10. East-West Design and Test Symposium Model of Diagnosis Process M – table of faults T – test set F – defects set V – vector of experimental check Acquisitionofthe CNF Transformation CNF to DNF Modelling for diagnosis specification

11. East-West Design and Test Symposium Modelling for diagnosis specification Detection of all rows, which correspond to zero of the experimental validation vector for nulling of all 1-coordinates. Detection of all columns, which have zero values of rows, coordinates with zero state of vector V. Removal the rows and the columns, which have only zero coordinate values. Creating CNF by one values of VEC and its simplification Without using this method:

12. East-West Design and Test Symposium The program module 1 Installation of elements and terms quantity Contains a prospective defective term (for conditional diagnosing F-IP) Diagnosis specification analyzing values of outputs. Allows to simplify the CNF preliminary Preliminary simplification of the fault Quantity of analyzed outputs The initial faults table Transformation of CNF to DNF Values of the elements specifying influence on value of Y output

13. East-West Design and Test Symposium The program module 2 Initial data in the program are: • the table that Characterizes the elements influencing at output result; • methods which will be applied to simplification of the faults table. • Initial faults table; • Quantity of analyzed outputs; • Installation of elements and terms quantity; Resultants data are: • Status of the faults table at each stage of sounding in control points (1); • Value of the defects combination at each stage of sounding in control points (2); • Quantity of necessary stages of sounding for result reception at use of consecutive and parallel choice of control points (3); 1 1 2 2 3

14. East-West Design and Test Symposium The program module 3 N - maximum quantity of no simplified DNF terms; Q - computing complexity of transformation of CNF to DNF and its simplifications; V – experiment check vector value; n - quantity of test sets; m - quantity of the elements participating in experiment; Ni - quantity of individual elements in the test set number i.

15. East-West Design and Test Symposium Methods of FPGA Components Repairing 2 Presenter: Eugenia Litvinova

16. East-West Design and Test Symposium Algebra-logical method for FPGA components repair 1 • The crystal topology is presented by the matrix of cells • scaled on horizontal and vertical integers figures (p*q); • Each cell MIJ has n2 logic blocks; • The matrix has any number of defects equal k; • In each cell can be no more than n2 logic blocks.

17. East-West Design and Test Symposium Algebra-logical method for FPGA components repair 2 Algorithm

18. East-West Design and Test Symposium Algebra-logical method for FPGA components repair 3 Criteria calculation # 1 - maximum (minimum) index of row j, behind which there are no co-ordinates with value "1". - maximum (minimum) index of column i, behind which there are no co-ordinates with value "1". - quantity of defect blocks. N – quantity of used reserve cells. # 2 Step 1. The counter of zero co-ordinates, the counter of repair cells number nulling: j=0, Q=0, parameter K=1 and criteria value for the current column. Step 2. Consecutive scanning of vector cellstofirstonewith «1» value. Step 3. Consecutive detour of cells on a column (row). If expression =0 is true – K=K+1, otherwise Q=Q+K. Step 4. Iftheconditionistrue - endofrowprocessing, otherwise – transitiontostep 3

19. East-West Design and Test Symposium Example of FPGA repair 1 n=3 - dimension of one covering cell; p=q=5*n=15 - quantity of horizontal and vertical cells dimension n*n;

20. East-West Design and Test Symposium Example of FPGA repair 2 Criteria calculation #1 Criteria calculation #2 • Result: it is more rational to cover on columns. • Result: it is more rational to cover on columns.

21. East-West Design and Test Symposium Example of FPGA repair 3 Method efficiency Real result: Rows – 19 cells Columns - 18 p n n=3 p=24 q=24 N=200 q Criteria #1 Criteria #2

22. East-West Design and Test Symposium The program module 1 The primary matrix, that define position of defective FPGA components; Dimension of one covering cell; Quantity of horizontal cells dimension n*n; Quantity of vertical cells dimension n*n;

23. East-West Design and Test Symposium The program module 2 Reception of the horizontal and vertical modified matrixes; Optimum covering criteria calculation; Construction of a horizontal and vertical matrix from modified where incorporated cells which it is necessary to cover by reserve one's - have value "1"; The quantity of cells necessary for defective components covering on horizontal and a vertical direction are calculated.

24. East-West Design and Test Symposium Conclusions Suggested methods of diagnosis: algebra-logical and vector-logical offers in the design and testing of digital systems in the crystals mathematical apparatus, which is capable to carry out the diagnosis of defective components, if there exist a pre-built faults table. New matrix method for defects diagnosis in digital system, which is characterized by normal disjunctive form and faults table, which makes it possible to obtain a complete and minimal combinations of multiple faults Choice one of two strategies for rows and columns detour of logic blocks matrix on the basis of structurization criteria is offered.

25. East-West Design and Test Symposium Thank You for Your Attention! Moscow, Russia, September 18-21, 2009