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CoDeveloper Overview Updated February 19, 2004

CoDeveloper is a software tool that targets hardware/software programmable platforms, supporting traditional processors and programmable hardware elements. Compatible with popular development frameworks, it provides crucial support for hardware/software interfaces and efficiently maps applications to platforms.

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CoDeveloper Overview Updated February 19, 2004

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  1. CoDeveloper OverviewUpdated February 19, 2004

  2. Introducing CoDeveloper™ • Targeting hardware/software programmable platforms • Target platforms feature a mix of traditional processor elements and programmable hardware elements • Altera, Xilinx, and other key platforms • Emphasizing software-oriented design methods • Compatible with familiar software development frameworks • Including Visual Studio, Codewarrior, GCC, Eclipse, etc. • Providing crucial support for hardware/software interfaces • Tools efficiently map the application to the platform • Programming model supports highly parallel hw/sw systems • Providing more than just C to hardware compilation!

  3. Impulse Cdesign files Impulse Platform Libraries CoBuilder™ RTL generator CoBuilder™ architecture generator CoBuilder™ library generator Impulse hardware libraries Impulse software libraries GeneratedHDL files GeneratedHDL files Generatedsoftware libraries FPGAsynthesis tool Targetcross compiler CoDeveloper Design Flow Complete software/hardware applicationready to implement on target platform

  4. Accelerating Applications: How? • Identify and exploit low-level parallelism in standard C • Examples: pipeline and/or unroll loops, schedule assignments, generate hardware for C processes • Advantage: can accelerate legacy C algorithms, inner code loops, etc. and reduce need for manual optimization • Encourage and assist programmers in the use of alternate, more efficient parallel programming techniques • Support the language they are most familiar with (ANSI C) • Provide libraries, tools and examples for parallel programming • Advantage: best way to address system-level optimizations • There is where the biggest performance gains are found!

  5. Application Domains • Applications requiring repetitive computations at very high speed • Dataflow-oriented, high degrees of parallelism • Pipelined algorithms (e.g. filters) • For processing streams of data in real time • Imaging • Communications • Digital Signal Processing (DSP)

  6. RISC FPGA Impulse C Applications RISC FPGA Targeting Programmable Platforms Two categories: • Standard RISC processorplus FPGA • FPGA withembedded (“soft”)RISC processor

  7. Who Makes These Platforms? • Altera: Nios™ processor • Cyclone and Stratix FPGA families • Xilinx: MicroBlaze™, PowerPC™ processors • Virtex and Spartan FPGA families • Quicklogic: QuickMIPS™ • Others yet to be announced • This is a HOT area in the FPGA industry

  8. S/Wprocess H/Wprocess S/Wprocess H/Wprocess H/Wprocess H/Wprocess Mapping Applications to Platforms FPGAhardware resources Bus interface Embedded processor This is nota trivial task! S/Wprocess H/Wprocess H/Wprocess S/Wprocess H/Wprocess H/Wprocess FPGA-based platform

  9. S/Wprocess H/Wprocess S/Wprocess H/Wprocess H/Wprocess H/Wprocess S/Wprocess H/Wprocess H/Wprocess S/Wprocess H/Wprocess H/Wprocess Example: Altera Nios Impulse Capplication FPGAhardware resources Avalon interface NIOS processor Cyclone or Stratix FPGA

  10. S/Wprocess H/Wprocess S/Wprocess H/Wprocess H/Wprocess H/Wprocess S/Wprocess H/Wprocess H/Wprocess S/Wprocess H/Wprocess H/Wprocess Example: Xilinx MicroBlaze Impulse Capplication FPGAhardware resources MicroBlazeor PowerPC processor OPB and/or FSL interface Virtex or Spartan FPGA

  11. How Is This Done Today? • Software engineer writes code (typically C) for embedded processor • High design productivity using high-level languages • But low-performance results (processors are SLOW) • Hardware engineer writes low-level HDL code for FPGA or ASIC portion • Very low design productivity (1/10th or less of the s/w eng) • But high performance results (hardware runs FAST) • System designer is the hardware/software mediator • Specifies hardware/software interfaces and locks down the design to reflect hardware design lead-times

  12. How Does CoDeveloper Help? • Reduces or eliminates the need to re-implement software routines as low-level hardware • Automates the process of creating hardware/software interfaces • Provides a software programming model appropriate for the target platform

  13. Impulse Platform Libraries Impulse Cdesign files Visual Studio™CodeWarrior™GCC, etc. GenerateRTL Generatehardware interfaces Generatesoftwareinterfaces HDL files HDL files Software libraries Altera Quartus,Xilinx ISE, otherFPGA tools Nios compiler,MicroBlazecompiler,others Impulse for HW/SW Codesign

  14. S/Wprocess H/Wprocess S/Wprocess H/Wprocess H/Wprocess H/Wprocess S/Wprocess H/Wprocess H/Wprocess S/Wprocess H/Wprocess H/Wprocess From C Application to FPGA Platform • Platform librariessupport existingembedded compilerenvironments • Automatic generationof hardware/softwareinterfaces is optimizedfor target platforms • FPGA hardwareis automatically createdfrom C languageprocesses The result?Accelerated softwarewith minimal need forhardware or FPGAdesign knowledge

  15. Impulse Cdesign files Legacy C algorithms Impulse Platform Libraries Impulse Design Assistant Impulse Simulation Libraries CoBuilder™ RTL generator Targetcross compiler Hoststandard C compiler HDLdesign files GeneratedHDL files Target download binary Host simulation executable HostC debugger FPGAsynthesis tool CoValidator™ HDL simulator Target ISS and/ordebugger CoMonitor™ application monitor CoWave™ waveform viewer CoDeveloper™ Tool Flow

  16. Impulse C • Based on Streams-C from Los Alamos National Labs • Dataflow-oriented C language extensions for highly parallel systems • HDL generation for FPGA elements • C language or other code generation for processor elements • Impulse improvements include: • Language redesign (standard ANSI C with Impulse C library functions) • Redesigned scheduling and code generation for FPGA targets • Application Manager, Application Monitor and full compatibility with Visual Studio and other standard development/debugging environments

  17. H/W process S/W process S/W process H/W process H/W process Impulse C Programming Model • Modified Communicating Sequential Process (CSP) model • Buffered communication channels (FIFOs) to implement streams • Supports dataflow and message-based communications between functional units and local or shared memories • Supports parallelism at the application level and at the level of individual processes (via automated scheduling/pipelining)

  18. Shared memory reads/writes C language process Stream inputs Stream outputs Signal inputs Signal outputs Software processes set up data and perform non time-critical functions App Monitor outputs Hardwareprocesses are independently synchronized and perform most of the work Impulse C Processes

  19. Impulse Cdesign files Impulse Platform Libraries CoBuilder™ RTL generator CoBuilder™ architecture generator CoBuilder™ library generator Impulse hardware libraries Impulse software libraries GeneratedHDL files GeneratedHDL files Generatedsoftware libraries FPGAsynthesis tool Targetcross compiler CoBuilder Compilation Process Complete software/hardware applicationready to implement on target platform

  20. Application software(embedded processor application) Impulse C application, compiled using standardC cross-compiler and related tools Impulse C function library for stream andsignal h/w-s/w interfaces Impulse C runtime library Processor/FPGA interface(s/w driver generated by CoBuilder) Interface routines (drivers) automaticallygenerated by CoBuilder for the selected platform FPGA platform bus Standard bus specified for target platform FPGA hardware wrapper(generated by CoBuilder as HDL) Bus interface wrapper automatically generatedby CoBuilder for the selected platform Impulse C hardware processes(generated by CoBuilder as HDL) Impulse C h/w processes, compiled to HDL byCoBuilder and synthesized using standard tools Impulse C hardware library Library of h/w interface components Impulse C H/W-S/W interfaces

  21. Impulse C Case Study 3DES Encryption(Xilinx Microblaze platform)

  22. Case Study: 3DES Encryption • Use publicly available 3DES source code • Written by Phil Karn (www.ka9q.net) • Not written to take advantage of parallel programming techniques (optimized for typical processor targets) • Make minimal changes in support of streams-based communication • Use stream reads/writes for data blocks and keys • Simulate legacy and Impulse C versions using same data • Build one simulation executable containing both versions • Compile to hardware, compare results again • Legacy version runs in uP, Impulse C version runs in hardware

  23. FPGA gates H/W encrypt Producer(random data) Consumer(compare resultsand speed) S/W encrypt(legacy C) Embedded processor “Platform” FPGA Application Structure (HW Test) Reference/prototype board

  24. 3DES Desktop Simulation • Complete 3DES application compiled using standard tools • Legacy C and Impulse C compiled as one application • Verified using both Visual Studio .NET and GCC/GDB • Application Monitor used to debug and improve stream data movement • Example: identified throughput increase possible through simple increase in buffer sizes (double-buffer inputs)

  25. H/W encrypt(Impulse C) H/W decrypt(Impulse C) Producer(from file) Consumer(display results) S/W encrypt(legacy C) S/W decrypt(legacy C) 3DES Desktop Simulation

  26. Desktop Simulation CoDeveloper Application Monitor

  27. Impulse Platform Libraries Impulse Cdesign files Visual Studio™CodeWarrior™GCC, etc. GenerateRTL Generatehardware interfaces Generatesoftwareinterfaces HDL files HDL files Software libraries Altera Quartus,Xilinx ISE, otherFPGA tools Nios compiler,MicroBlazecompiler,others Compiler Flow

  28. Results (Virtex II FPGA) • MicroBlaze clock running at 100MHz • 3DES algorithm clocking at 24MHz • Performance (1000 blocks): *Includes I/O overhead: 11% • Clock cycles to process one block: 149 (not including I/O overhead) • 36X speedup over software-only version

  29. Summary • CoDeveloper and Impulse C provide: • Programming model and tools supporting hardware / software codesign for programmable hardware targets • Compiler technologies (CoBuilder) allowing software processes to be compiled directly to hardware. • CoDeveloper is a software-oriented solution • Designed (and priced) to appeal to software developers, not just leading edge FPGA experts • Designed to operate in conjunction with existing software development tools and tool flows • Designed to accelerate hardware/software prototypes and products

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