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ARM interrupts and the VIC

ARM interrupts and the VIC. Interrupt. Interrupt. Interrupt return. Interrupt code. Main program code. ARM interrupts. ARM runs in 1 of 6 modes each mode has (some) unique registers mode is available to outside world (fi: for a memory managment unit – not in LPC2106)

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ARM interrupts and the VIC

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  1. ARM interrupts and the VIC Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology

  2. Interrupt Interrupt Interrupt return Interrupt code Main program code Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology

  3. ARM interrupts • ARM runs in 1 of 6 modes • each mode has (some) unique registers • mode is available to outside world (fi: for a memory managment unit – not in LPC2106) • current mode is in the CPSR register • 2 ‘normal’ interrupts: IRQ, FIQ Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology

  4. N Z C V ARM User Programming model mode 0 31 31 0 31 0 r0 r8 CPSR r1 r9 Status register r2 r10 r3 r11 r4 r12 r13: stack pointer r14: link register r5 r13 r6 r14 r7 r15 (PC) Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology

  5. All ARM registers  Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology

  6. interrupt start • switch to the interrupt mode (IRQ or FIQ) (this switches to the new set of registers!) • copy PC to LR • copy CPSR to SPSR • set PC to start of interrupt code (fixed) notes: • Almost the same as a procedure call (BL) • no use of the stack • No (automatic) saving of registers Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology

  7. IRQ • ‘normal’ interrupts • Private LR (of course) • Private SP • no other private registers (must save users registers) Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology

  8. FIQ • typically used for ‘simple & fast’ processing • Private LR (of course) • Private SP • Private R6 .. R12  • Low latency: • no need to save user’s registers • no need to initialise FIQ registers! Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology

  9. VIC • Vectored Interrupt Controller • between interrupt sources and the ARM core • handles: priorities and vectoring http://www.arm.com/pdfs/DDI0181E_vic_pl190_r1p2_trm.pdf Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology

  10. interrupt priorities • FIQs • Vectored IRQs • Non-vectored IRQs While the code for an interrupt is running lower interrupts are blocked  The interrupt code must inform the VIC when its done! Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology

  11. vectors Each • FIQ • vectored IRQ has a unique vector. In most cases this will be the start address of the code that handles the interrupt. All non-vectored IRQs share one vector, the interrupt code must inquire which interrupt has occured. Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology

  12. interrupt sources • 32 sources possible • 16 hardware sources implemented on an LPC 2106 Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology

  13. forcing, masking, assigning Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology

  14. forcing I Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology

  15. masking I Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology

  16. IRQ /FIQ assigning I Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology

  17. FIQ Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology

  18. FIQ I Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology

  19. non-vectored IRQ Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology

  20. non-vectored IRQ I Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology

  21. vectors Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology

  22. vectors • 16 vector slots • 0 has highest priority, 15 lowest • each slot contains • enable bit • the interrupt source (0..31) • the vector address (32 bits) Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology

  23. vectors I Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology

  24. IRQ arbitration Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology

  25. IRQ arbitration I Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology

  26. interrupt end This is not mentioned in the Philips manuals  Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology

  27. interrupt configuration • probably: reserve and set the interrupt stack • make sure the hardware vector points to your code • configure the peripheral to generate interrupts • enable the interrupt source • select FIQ or IRQ • (vectored) set source, enable, vector • (non-vectored IRQ) set default vector • enable interrupts Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology

  28. set interrupt stack ldr r2, = … mrs r0, cpsr @ Original PSR value bic r0, r0, #0x1F @ Clear the mode bits orr r0, r0, #0x12 @ Set IRQ mode bits msr cpsr_c, r0 @ Change the mode mov sp, r2 bic r0, r0, #0x1F @ Clear the mode bits orr r0, r0, #0x13 @ Set Supervisor bits msr cpsr_c, r0 @ Change the mode Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology

  29. interrupt vectors ldr pc, =ResetHandler @ reset vector ldr pc, =ResetHandler @ undefined instruction ldr pc, =ResetHandler @ software interrupt ldr pc, =ResetHandler @ prefetch abort ldr pc, =ResetHandler @ data abort ldr pc, =ResetHandler @ reserved ldr pc, [pc, #-0xFF0] @ IRQ. load vector @ from VICVectAddr ldr pc, =ResetHandler @ FIQ Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology

  30. interrupt code • (probably) save registers • do what you have to do • clear the interrupt source • write to VicVectAddr • return: subs pc, lr, #4 Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology

  31. enable / disable interrupts Why? • protect data that is used by both main and interrupts • protect code that must execute with a fixed timing Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology

  32. enable / disable interrupts __disable_interrupts: mrs r0, CPSR orr r0, r0, #0x80 @ disable IRQ interrupts msr CPSR_fsxc, r0 mov pc, lr __enable_interrupts: mrs r0, CPSR bic r0, r0, #0x80 @ enable IRQ interrupts msr CPSR_fsxc, r0 mov pc, lr Hogeschool van Utrecht / Institute for Computer, Communication and Media Technology

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