Interrupts and Exceptions

1. Interrupts and Exceptions CNS 4510

2. Interrupts • Two types • Synchronous • control unit issues interrupt after instruction has completed • Sometimes called exceptions • Asynchronous • interrupts generated by other hardware devices at arbitrary times with respect to the CPU clock signals

3. Interrupts • Interrupts • Keystrokes • read from disk finished • interval timer event • Exceptions • divide by zero • page fault • request for OS service

4. Interrupts • An interrupt is an event that alters the sequence of instructions executed by a processor

5. Interrupts • Divert the normal flow of processing • What happens during an interrupt • Save the current value of the PC • jump to new interrupt instruction

6. Interrupts are not processes • Key difference between process switching and interrupt handling • Interrupts are kernel control paths that run on behalf of the same process that was running when the interrupt occurred • interrupt handlers are lighter than process • less context • less setup/teardown time

7. Interrupts are sensitive • They come at any time • user mode • kernel mode • Kernel wants to get the interrupt out of the way asap. • Example – block of data ready from disk • Right in middle of context switch • Acknowledge presence of data • Write data • Interrupts divided into two parts • top half (acknowledge interrupt) • bottom half (handle the interrupt)

8. Nested Interrupts • Interrupts could happen at any time • Could also happen when interrupt handlers are running • This should be allowed as much as possible cuz it keeps the IO devices busy • critical sections need to be protected

9. Types of Interrupts • Maskable interrupts • Interrupts coming in on an IRQ • IO devices • Non-maskable interrupts • Hardware failures

10. Exceptions • Processor detected exceptions • Faults • Example: pagefault • Traps • Used to notify a debugger • Abort • A serious error occurred and the control unit is in trouble, can’t store in the pc register the precise location of the instruction that generated the interrupt • Programmed exceptions • Also called software interrupts • triggered by int, int3, into, and bound instructions • Usually used to implement system calls

11. IRQ • Interrupt ReQuest • All IRQ lines are connected to the input pins of a hardware circuit called the interrupt controller • Each IRQ line can be selectively disabled • Disabled interrupts are not lost • They are sent as soon as the controller is enabled

12. Interrupt Controller • 1. Monitors the IRQ lines checking for raised signals • 2. If a raised signal occurs • convert the signal received into a corresponding vector • store the vector in an Interrupt Controller I/O port so it can be read via the data bus • send a raised signal to the processor INTR pin • wait until the CPU acknowledges the interrupt signal by writing into one of the Programmable Interrupt Controllers (PIC) I/O ports • when this occurs – clear the INTR line • 3. goto step 1.

13. Masking Interrupts • Selective disabling of IRQ lines is not the same as global masking/unmasking of maskable interrupts. • when the interrupt flag is clear each maskable interrupt is temporarily ignored by the cpu

14. Intel 80x86 Exceptions • 0 - Divide Error • divide by 0 • 1- Debug • Debug register or T flag is set • 2- Not used (NMI) • 3- Breakpoint • int3 (breakpoint) instruction • 4. Overflow • into (check overflow instruction) and OF flag is set • 5. Bounds check • bound instruction is executed with operand outside of valid address • 6. Invalid opcode • 7. Device not available • Escape, MMX, or XMM instructions fave been executed with TS flag set • 8. Double fault • when two exceptions cannot be handled at the same time • 9- Coprocessor segment overrun • problems with external math coprocessor

15. Intel 80x86 exceptions • 10 Invalid TSS • context switch to process with invalid TSS segment • 11 Segment not present • reference to segment not present in memory • 12 Stack segment • instruction exceeded the stack segment limit • 13 General protection Fault • protected mode violated • 14 page fault • addressed page not in memory • 15 reserved • 16 Floating-point Error • 17 Alignment check • address not a multiple of 4 • 18 Machine check • machine-check mechanism detected a cpu or bus error • 19 SIMD floating point

16. Interrupt Descriptor Table • Associates each interrupt or exception vector with the address of the corresponding interrupt or exception handler • Must be initialized before kernel enables interrupts • controlled by the idtr register • base address • limit address

17. Interrupt Descriptor Table • May include three types of descriptors • Task gate • includes the TSS selector of the process that must replace the current one. (not used by linux) • Interrupt gate • Holds an Interrupt exception handler • Trap gate • same as interrupt gate except doesn’t modify the if flag. • Linux uses interrupt gates to handle interrupts and trap gates to handle exceptions

18. Hardware Handling of Interrupts • cs and eip registers contain next instruction to be executed • Before executing an instruction cpu checks if an interrupt occurred • If one did occur the control unit does the following: • 1. Determines the interrupt vector • 2. Determine the type of entry • 3. Get the base address of the segment that includes the interrupt handler • 4. Be sure the interrupt was issued by an authorized source • 5. Check to see if a change of privilege is taking place • 6. Save appropriate context • 7. Save hardware error code on the stack • 8. Load appropriate context from the interrupt table • 9. Jump to the interrupt handler

19. Hardware Handling of Interrupts • On execution of an iret • 1. Load registers with values stored on the stack • 2. If privilege was changed • Load ss and esp registers from stack • return to old privilege level • 3. Fix segment registers