Enhanced Resist and Etch CD Control by Design Perturbation

1. #SB=1 #SB=2 #SB=3 #SB=4 • Typical etch dummy rule: fixed rule for active-to-etch dummy spacing • SAEDM: change rule of active-to-etch dummy spacing • Calculate left poly-to-dummy and right poly-to-dummy spacings to insert Assist Features and Etch Dummies simultaneously • Insert Etch Dummies with asymmetric left- and right- active-to-dummy spacings L R forbidden pitch Before SAEDM (SRAF missing: L=R) Forbidden pitch Cell boundary R L After SAEDM (SRAF inserting: L R) Before AFCorr After AFCorr Poly Active SRAF Etch dummy Puneet Gupta*, Chul-Hong Park† and Andrew B. Kahng*†‡ * Blaze DFM, Inc. † UCSD, ECE Department ‡ UCSD, CSE Department Enhanced Resist and Etch CD Control by Design Perturbation Abstract Etch Dummy Insertion Problem Technique 1: SAEDM • Etch dummy features are used to reduce CD skew between resist and etch processes and improve printability. However, etch dummy rules conflict with SRAF insertion because the two techniques each require particular spaces of poly-to-assist, active-to-etch dummy, etc. • We first present a novel SRAF-Aware Etch Dummy Method (SAEDM) which optimizes etch dummy insertion to make the layout more conducive to assist-feature insertion after etch dummy have been inserted. • We also describe a novel dynamic programming-based technique for etch-dummy correctness (EtchCorr) which is used in combination with the SAEDM for detailed placement. • EtchCorr placement with SAEDM can achieve up to 100% reduction in number of cell border poly geometries having forbidden pitch violations. • These techniques extend existing RET techniques to meet the ITRS CD tolerance spec by interactions with design. Hence, our techniques can delay the need for radically new RET or equipment solutions. Maximum allowable etch dummy space (MAEDS) Poly Active SRAF Etch dummy • Etch dummy features are placed to the outside of active-layer regions • Etch dummy features are inserted between primary patterns with certain spacing to reduce etch skew between resist and etch process • Maximum allowable etch dummy space (MAEDS) is determined by allowable CD skew of resist and etch Technique 2: EtchCorr Placement Correctness for Etch Dummy Algorithm Approach: Dynamic Programming (DP) Design and Test Flow • Key Idea:Change whitespace distribution of standard-cell placement  best printability • Maximize number of assist features (AFCorr) • Optimize location of etch dummies (EtchCorr) • AS (ES): sets of feasible spaces between two gates that allows insertion of required assist features (etch dummies) Lithography & etch model generation Modified library & netlist • “Etch-Correctness” solved by the following DP recurrence: Post-placement (AFCorr + EtchCorr) Typical Design Flow Forbidden pitch, CD slope and skew of resist and etch Placement Route Route • Printability • #Etch dummy and #SB • EPEs of resist and etch • Performance • Delay, OPC run time Assist and etch dummy corrected GDSII • Cost(a;b) = the cost of placing cell a at placement site number b • |(x_a - b)| = placement perturbation of cell "a" • AFCost, EtchCost: printability deterioration of resist and etch CDs • SRCH:Maximum allowable change in location of a standard-cell instance • λ: weight between goals of placement preservation and printability benefit • α and β: user-defined weights for AFCost and EtchCost Typical GDSII SB OPC OPCed GDS SAEDM • SB Insertion • Model-based OPC • Our novel design flow adds steps of forbidden pitch extraction, SAEDM AFCorr and EtchCorr to typical design flow • Minimize EPE (Edge-Placement Error) and maximize #dummy and #SB Summary and Ongoing Work Optical and Etch Simulation Experimental Results • EtchCorr placement perturbation with SAEDM can achieve up to 100% reduction in number of cell border poly geometries having forbidden pitch violations. The corresponding reduction in EPE is up to 98% (resist CD) and 97% (etch CD) • SB count and etch dummy counts, which indicate less through-focus CD variation and etch skew, increase up to 10.8% and 18.6%, respectively • Increases of data size, OPC running time and maximum delay due to EtchCorr are within 3%, 4% and 6%, respectively • Runtime of EtchCorr placement perturbation is negligible (~5 minutes) compared to running time of OPC (~2.5 hours) • Ongoing research: • Investigate other perturbation objectives such as weighting of perturbation cost by cell timing criticality • Develop methodologies for “correct-by-construction” standard cell layouts that are always EtchCorrect and AFCorrect in any placement scenario • Number of total SRAFs and etch dummies increases due to EtchCorr • Reduction in Forbidden Pitch Count of resist process  57%-94% with SAEDM and 77%-100% with SAEDM + EtchCorr • Reduction in Forbidden Pitch Count of etch process  73%-97% with SAEDM + EtchCorr • After whitespace adjustment, additional SRAFs can be inserted to avoid forbidden pitch  resist image (verifiable by simulation) is better • Large resist-to-etch skew in isolated patterns necessitates etch dummy insertion