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sTGC trigger demonstrator

sTGC Trigger Demonstrator ATLAS Israel Annual Meeting 3 0 December 2012 Lorne Levinson, Julia Narevicius, Alex Roich, Meir Shoa, Vladimir Smakhtin. sTGC trigger demonstrator. Demonstrate t rigger path only from chamber to Sector Logic input

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sTGC trigger demonstrator

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  1. sTGC Trigger DemonstratorATLAS Israel Annual Meeting30 December 2012Lorne Levinson, Julia Narevicius,Alex Roich, Meir Shoa, Vladimir Smakhtin L. Levinson, sTGC Trigger Demonstrator

  2. L. Levinson, sTGC Trigger Demonstrator

  3. sTGC trigger demonstrator Demonstrate trigger path only from chamber to Sector Logic input • Not for studying detector properties and ultimate resolution:ToT is non-linear and saturates, probably not used for final ASD • use cosmic rays • BNL VMM1 ASD: 32 ASDs for strips, 12 for pads • Strips: convert ToT to charge by measuring length of ToT with 1nsec sampling: • Emulates future “TDS” = Trigger Data Serializer ASIC • peak-to-time would be the sameflash ADC would deserialize with 5nsec /bit • Serial output at 6.25Gb/s • Pads: Simple trigger: dual 3-out-of-4 coincidence logic • Serial transmission of pad trigger data to TDS (but without BCID assignment) • Centroid finding, centroid choosing, track vector calc • Latency measurement L. Levinson, sTGC Trigger Demonstrator

  4. Not demonstrated • Because ToTs are saturated, no attempt to get precision centroids: • No Router, instead there is direct 6Gb/s link from TDS to centroid finder via twinax cables • No readout of VMM L. Levinson, sTGC Trigger Demonstrator

  5. L. Levinson, sTGC Trigger Demonstrator

  6. Pad over-lapping for 3-out-4 coincidence • Shown above: pad overlap in a pair of layers • Three rows of 7 pads. Two rows of 8 pads • The second pair of layers in the multiplet is the same. • 37 pads per pair of layers • Total 4x37 = 148 pads • Trigger looks in 12ns windows (six 2ns samples): if 3 or more pads are non-zero, a trigger is generated L. Levinson, sTGC Trigger Demonstrator

  7. sTGC Trigger Demo-1 FPGA board Power module Trigger Data Serializer FPGA 16+12 ASD connectors Pad trigger/ centroidFPGA 10G Quad fibre interface 10G twinax*4 connector Ethernet readout L. Levinson, sTGC Trigger Demonstrator

  8. Status • PCB boards being tested • FPGAs correctly receives non-standard LVDS from VMM ASDs • Firmware done, not tested, but much the same as for Demo-0 • Reassembling pad signal extraction and ASD adapter boards … there are both “left” and “right” VMM boards • Board to bring pad signals to edge of chamber for 2 or 3 rows of pads • Boards to adapt VMM ASDs to the strips on edge of chamber • Boards to adapt VMM ASDS to the board that extracts the pad signals • We have 46 VMMs in Israel, 44 needed for full test • Configuration system, HW and SW, being built for up to 48 ASDs • Getting results for Milestone Meeting will be tight, depends on • no disasters with the PCB boards • understanding of 6.25Gb/sec serial links (deserializers) • We have backup parallel 6Gb/s links if problems with serial links L. Levinson, sTGC Trigger Demonstrator

  9. Configuration of 12x4 VMM ASDs L. Levinson, sTGC Trigger Demonstrator

  10. Latency  sTGC The table shows the latency from the interaction point, through the precision strip trigger logic for the Inner Layer to the Sector Logic in USA-15. We take as a model the Xilinx Virtex6. All times are estimates except that for the centroid finder which has been measured. NSW Trigger, TDAQ Week Oct 2012

  11. The end L. Levinson, sTGC Trigger Demonstrator

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