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Paper Report An Enhanced Debug-Aware Network Interface for Network-on-Chip

Paper Report An Enhanced Debug-Aware Network Interface for Network-on-Chip. Feng-Xiang Huang. International Symposium Quality Electronic Design (ISQED), 2012 13th M. H Neishaburi, Zeljko Zilic, McGill University, Quebec Canada. Abstract.

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Paper Report An Enhanced Debug-Aware Network Interface for Network-on-Chip

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  1. Paper ReportAn Enhanced Debug-Aware Network Interface for Network-on-Chip Feng-Xiang Huang International Symposium Quality Electronic Design (ISQED), 2012 13th M. H Neishaburi, Zeljko Zilic, McGill University, Quebec Canada.

  2. Abstract • As emerging System on Chips (SoCs) tend to have many cores, the interactions among cores through functional interconnects such as bus or Network on Chips (NoCs) are and on-chip communication has accentuated the need to enhance traditional debug methods for SoCs. In this paper, we propose a new debug aware Network Interface (NI). The proposed debug aware NI monitors the transactions issued by processing elements and extracts the global order of transactions from the local partial order of transactions. Moreover, the proposed interface provides a mechanism for a cross-triggers debugging. The modules in charge of cross-trigger debugging monitor the transaction issued by connected IP blocks and invoke appropriate debug operations at the right time. Trace data and trigger events are extracted and routed to Shared Direct Memory Access Unit( SDMAU). SDMAU combines debug traces from different NIs. The major benefits of using our proposed mechanism over traditional techniques are as follows: 1) the proposed debug aware NI can generate non-intrusively the global states of a system that involve multiple clock domains and enable validation of global properties, 2) It can detect, mark and bypass severe fault conditions such as deadlocks resulting from design errors or electrical faults in real time, 3) SDMAU maintains an efficient transfer of trace data to an external memory and there is no need for a large internal trace memory.

  3. Related Work Effcient Network Interface Architecture for Network-on-Chips • NORCHIP, 2009, Finland Runtime Checking of Serializability in Software Transactional Memory[5] [24] [25] [26] • Make Status register of specific core • visible • Time-stamping mechanism • Intrusive • Reduces the system throughput An Enhanced Debug-Aware Network Interface for Network-on-chip • ISQED, 2012,Canada

  4. What is the problem • Communications among cores (bus interface/ memory controller/ up) • Distributed of application on NoC • Global vs. Local (transaction ordering) • Design vs. electrical error • Deadlock • Livelock • Race condition • Data Inconsistency

  5. Proposed Method • a debug-aware NI Character • Communication port/ debug interface • Non-intrusively & Multi clock domain • Compatible AXI • Detect & bypass fault • Efficient transfer of trace data to external memory Fig. AXI-Compatible NoC-Based System

  6. Proposed Method- a debug-aware NI • Master Side NI • Request • Slicer unit • Response • Merger unit • Local Debug Unit (LDU) • Reorder Buffer • Tran. Table • SDMAU • Trace info. to external trace memory • Cross Triggers Packetizer to Router Router de_Packetizer from Router Transaction  packet (header/data/tail) 

  7. Proposed Method- a debug-aware NI • Master Side NI- Flow • LDU • Tran.Table & Reorder Table Fig. NI flow

  8. Proposed Method- a debug-aware NI • Master Side Network Interface • LDU • Tran.Table & Reorder Table Fig. NI flow

  9. Proposed Method- Cross tgrigger Unit • Cross Trigger unit • Inform LDU • Debug commands (stops, resume, trace, and etc.) • Trigger event generation(Debug Reg, Comparator)

  10. Experimental result • Environment • Assembly code: Factorial of consecutive number ranging from 1 to 100 • Inserted design errors in side NoC routers. • 94 fault pattern be detected by LDU • Observed that 60% data inconsistenc 32% deadlock Program (each iteration to check R0(result) by Cross trigger) ------------------------------- 1! 2! 3! … 100! Error Fig.

  11. Conclusions • Proposed • A debug aware NI that • Non-intrusively • Multiple clock domains system • Detects & bypass severe faulty condition (LDU && Trigger) • Compatible AXI protocol

  12. Comment • Error information • Figure 8 • Issue • Trace buffer/Table is widely used • Problem definition of behavior of SoC/NoC components • Specification definition

  13. DFD • Shadow registers/scan chains • (specific trgger/ • hardware checker) • On-chip trace buffers Design for Debug/Test 1 I-IP • u-processor • E-ICE • I-IP • IP • 1149.1 • 1500 • Nexus • Memory • BIST • Bus • Protocol Check • Protocol Tracer • Debug/Test Platform • Prof. Li. • Dedicated hardware • I-IP • Embedded logic analyzer • ChipScope • NoC • Network Interface μp 3 4 E-ICE Protocol Check Protocol Tracer Memory Memory Interface Router/Switch to Networking Memory Interface Memory Interface TAPC Network Interface 1149.1 cores 1500 cores WrapperICE I-IP IP IP OCP-IP NoC 2.6 TAM Controller 5.6

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