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ERD/ERM – IRC FxF Meeting

International Roadmap Committee. ERD/ERM – IRC FxF Meeting. Topics Tech Transfer to PIDS/FEP, Etc. Request to assess emerging research memory technologies. Jim Hutchby & Mike Garner Brussels, Belgium March 20, 2009.

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ERD/ERM – IRC FxF Meeting

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  1. International Roadmap Committee ERD/ERM – IRC FxF Meeting • Topics • Tech Transfer to PIDS/FEP, Etc. • Request to assess emerging research memory technologies Jim Hutchby & Mike Garner Brussels, Belgium March 20, 2009

  2. Introduction of technologies involving new materials requires ~12+ years from publication to manufacturing The last 4 – 6 years of this 12+ year total R&D period is development related to PIDS/FEP. The first 6 – 8 years is research related to ERM/ERD. Tech Transfer to PIDS/FEP

  3. Production Ramp-up Model &Technology Cycle Timing for III-V MOSFET Channel Replacement Materials 100M Production Research Development 200K 10M 20K 1M Transfer to PIDS/FEP (2009–2013) 2K Volume (Parts/Month) Alpha Tool Beta Tool Product Tool 100K Volume (Wafers/Month) 200 10K 1st 2Cos. Reach Product 20 First Conf. Papers 1K 2 0 24 -96 -72 -24 -48 Months 2011 2013 2015 2017 2019 2021 Source: 2009 ITRS – ERD/ERM/PIDS/FEP

  4. st Background / Practical 1 Practical Sponsor Entrant st Technology Infrastructure realization use 1 Customer Telegraph 1801 – 1823 1844 U.S. Gov. 1848 - Magnetic (Voltaic Pile) ( Schilling) (Morse) Telegraph Co 1856- Western Union Radio 1865 (Maxwell) 1888 (Hertz) 1897 British 1897 Wireless British 1896 ( Marconi) Post Telegraph&Signal Co Navy ( Marconi) Office Vacuum 1884 Fleming (1904) tube (Edison effect) De Forest 1907 U.S. Navy 1913 - AT&T WW I (1906) - triode Solid state 1906 AT&T 1907 Pickard Co WW I diode 1874 (F. Braun) 1900 ( Braun) 1941 Thomson-Houston 1940- Radar WWII 1942 AT&T, Sylvania current Program Disruptive Technologies in Electronics Transistor 1923 – 1939 1947-48 1951 AT&T 1951-52 - DoD TI, AT&T, GE, HP. Motorola Integrated 1944 – 1957 1958–R.Noyce, 1961 U.S. 1961 TI, Fairchild NASA, Circuit ( micromodule J. Kilby AirForce DoD program) Data 1889 Hollerith 1890 U.S. 1896 – Tabulating U.S. Processing Census Machine Co (from Census Bureau 1917 – IBM) Bureau Computer 1841 1946 - Eckert- U.S. ( Babbage) Mauchly Co Census 1945 - ENIAC 1946-1951 DoD (1951 – Remington) Bureau 1889 1951 IBM DoD Hollerith SRC/File name/ 4

  5. Time Gaps Solid State Diode T1 26 (1874-1900) T2 7 (1900-1907) T3 6 (1907-1913) Learning Period 13 years Vacuum Tube T1 20 (1884-1904) T2 9 (1904-1913) T3 6 (1913-1919) Learning Period 15 years Transistor T1 25 (1923-1948) T2 6 (1948-1954) T3 5 (1954-1959) Learning period 11 years Integrated Circuit T1 17 (1942-1959) T2 3 (1959-1961) T3 5(1961-1966) Learning Period 8 years Example: Solid State Rectifier Market production (Established Technology) Enabling Background exists Entrant Co formed Prototype built (Disruptive Technology) ‘Research Curve’ T2 T3 Transfer of Knowledge T1~ 20years ~10years Human Carrier Sponsor 1st Customer

  6. Development Cycle Times for Sample IC Technologies Year Initially Year Implemented Lag Tool or Technology Developed In Production Time Silicon Epitaxy 1960-61 1964 4 APCVD Silicon Nitride 1965 1967-68 2 Ion Implant 1969 1973 4 TiW Metalization 1969-70 1975-77 6 Schottky TTL 1970 1974-75 4 Charge-Coupled Device 1970 1981 11 Reactive Ion Etch 1975-76 1980 5 Polysilicon Emitter 1976 1984-85 8 Refractory Gate 1976 1983 7 SOI (via Ion Implant) 1978 1989 11 Trench Capacitor 1979 1986 7 Silicide 1978 1985 7 Lightly-Doped Drain 1980 1986 6 Average 6 years Source: Graydon Larrabee of Texas Instruments

  7. Study of R&D Latency for a few Semiconductor Technologies • CMOS • Giant Magnetoresistance (GMR) • Copper Interconnect • 193 nm photoresist • Magnetic RAM • EUV lithography Method. We used the following parameters: 1) The first publication on a given technology that appeared in the Science Citation Index database 2) The number of refereed articles in technical journals by year (Science Citation Index database) 3) The year of first production for a given technology

  8. CMOS 1981 – NationalNSC800 CMOS microprocessor 1972 – Toshiba CMOS calculator IC 1982 – Intel 80286 CMOS microprocessor 1983 – 1st CMOS DRAM (Intel) 1984 – Motorola 68020 CMOS microprocessor 12 years 1987 –CMOS at AMD 1969 – 1st publication

  9. Giant Magnetoresistance (GMR) 1997- 1st hard disk product using GMR heads (IBM) 1992 – MRAM concept 9 years 1988 - discovery of GMR effect

  10. 2000 – AMD x86 Cu-based microprocessor Copper Interconnect 12 years 1998 - Power PC 750 microprocessor(IBM) 1986 – 1st publication

  11. 193 nm photoresist 2001- 3M debuts 193nm photoresist chemicals 12 years 1989 – 1st publication

  12. Magnetic RAM 2004- 1st MRAM product projected (IBM/Infineon) 1992 – 1st publication 12 years

  13. Strained Silicon Example First Technology Paper: 1991, 1994 Addition to ITRS Roadmap: ~2001 Alpha Tool: TBD ITRS Production: 2003 (12 years) Technology Life: 3+ Generations New Technology Introduction Events • High κ (HfO2) Example • First Technology Paper: 1972 • Industry Interest ~1990 • Addition to ITRS Roadmap: 1997 • Alpha Tool: TBD • ITRS Production: 2010 (38 years) • Technology Life: 3+ Generations

  14. Conclusions The average time from first research paper on a technology typically using a new material to its’ first commercial production is about 12 years. • Research must have been in progress at least a few years before the first publication • Development of technology leading to first product is 4 – 6 years, based on the time gaps study [(T2+T3)/(T1+T2+t3) = 1/3 to 1/2] applied to the current study.

  15. ERD ITWGEmerging Research DevicesWorking GroupProposal for Assessing Technology Options for Emerging Research Memory Devices Jim Hutchby & Mike Garner Friday March 20, 2009

  16. ERD/ERM is seeking IRC guidance on whether we should conduct a review and assessment of emerging research memory technologies with the goal of recommending those most promising for detailed roadmapping and accelerated research. Assess technology capability of being scaled beyond the 15nm node. Identify precompetitive research required for top candidates to scale beyond the 15nm node Process will be completed in April 2010 with an oral report to the IRC in the Spring ITRS Meeting followed by a written report/recommendation to the IRC. Objective of IRC/ERD/ERM discussion of this request from Samsung, Hynix, and Micron

  17. Samsung, Hynix , and Micron proposed that the ERD/ERM identify memory technologies needing more focused support Proposal: ERD & ERM hold a workshop in April 2010 to review and assess emerging research memory devices Goal: Identify emerging research memory technologies that merit more detailed roadmapping and more focused research. Process: Same Process as the Logic Assessment in 2008 Champions present Pros, Cons and research needed for technology Friendly critic presents balanced assessment White paper prepared on each memory and circulated prior to the meeting Face to Face Presentations & Discussion Voting on Promising Technology Identify Critical Research Needed Assessment of Promising Emerging Memory Devices

  18. Straw Candidate Emerging Research Memory Technologies • Capacitive Memory • FeFET Memory • Resistive Memory • Nanoelectromechanical • STT MRAM • Thermal PCM • FUSE/Anti-FUSE • Nanowire PCM • Electrochemical Memory • Cation migration • Anion migration • Electronic Effects Memory • Charge trapping • Mott Transition • FE barrier effects • Macromolecular Memory • Molecular Memory

  19. DRAFT GOAL With the goal of providing input to resource allocation decisions, ERD/ERM WGs will conduct an in-depth review and assessment of specific emerging research memory devices to highlight the most promising device technologies for detailed roadmapping and acceleration of pre-competitive*research and development. (*Pre-competitive refers to those technologies capable of being scaled beyond the 15nm node.)

  20. DRAFT SCOPE The scope of the review of emerging research memory technologies will assess scalability beyond the 15nm node. • Identify precompetitive research needed to enable scaling beyond the 15nm node. • Assessment will encompass both stand-alone and, where different, embedded emerging research memory technologies.

  21. Draft Timetable

  22. Develop/decide process, milestones, timeline Develop invitation to advocates & opponents Introduction Potential of technology – fundamental limits Barriers – Fundamental vs. technological/engineering Evaluation Criteria / Benchmark memory technology Definition of maturing, high potential specific devices for roadmapping Readiness in ~ 5 - 10 years Proposed ERD/ERM WG Process for Assessing Candidate Emerging Research Memory Device Technology Options

  23. Identify Major emerging research memory technology candidates Strong technical proponent and opponent teams and their leaders Knowledgeable ERD/ERM mentor for each proponent team Key questions to be addressed by the teams Background materials for each technical candidate Issue invitations to team leaders and obtain their commitments Obtain a white paper & background materials from each candidate technology proponent team for ERD/ERM review Proposed ERD/ERM WG Process for Assessing Candidate Emerging Research Memory Device Technology Options

  24. REDO THIS SLIDE

  25. ERD/ERM WG rate and prioritize candidate emerging research memory technologies using a formal process prior to FxF meeting. Conduct a FxF review of categories with each proponent & opponent team making a presentation On second day of ERD/ERM FxF meeting, discuss/decide ERD/ERM’s recommendation of most promising emerging research memory technology options. Write & submit report to the IRC on ERD/ERM WG’s recommendations Proposed ERD/ERM WG Process for Assessing Candidate Emerging Research Memory Device Technology Options

  26. BACKGROUND SLIDES

  27. Develop/decide process, milestones, timeline Identify Major memory technology candidates Strong technical proponent and friendly critic teams and their leaders Knowledgeable ERD/ERM mentor for each proponent team Key questions to be addressed by the teams Background materials for each technical candidate Develop invitation to proponents & friendly critics Introduction Potential of technology – fundamental limits Barriers – Fundamental vs. technological/engineering Evaluation Criteria Definition of specific devices for roadmapping Readiness in 10-15 years Proposed ERD/ERM WG Process for Assessing Candidate Emerging Research Memory Device Technology Options

  28. Issue invitations to proponent and friendly critic team leaders and obtain their commitments Identify ERD/ERM Mentors – 1 per candidate memory technology Obtain a white paper & background materials from each candidate technology proponent team for ERD/ERM review ERD/ERM WG review candidate emerging research memory technologies using a formal process prior to FxF meeting to identify questions to be addressed in FxF meeting. Proposed ERD/ERM WG Process for Assessing Candidate Emerging Research Memory Device Technology Options

  29. Conduct a FxF review of categories with each proponent & friendly critic team making a presentation On second day of ERD/ERM FxF meeting, discuss/decide ERD/ERM’s recommendation of most promising emerging research memory technology options. Mentors will lead the discussion of their candidate technology Write & submit report to the IRC on ERD/ERM WG’s recommendations Proposed ERD/ERM WG Process for Assessing Candidate Emerging Research Memory Device Technology Options

  30. Decision Making & Majority Voting Scheme Each member of ERD WG will be given a maximum of X votes to use in voting for their top X choices among the candidate technologies (Majority Voting scheme) ERD/ERM WG members present in the FIRST DAY Workshop & the SECOND DAY meeting will be eligible to vote at SECOND DAY meeting, based on their personal technical judgment, independent of their corporate affiliation or regional representation, Only 0 or 1 vote can be cast for any candidate technology Member does not have to use all X votes, but cannot use more than X votes. All members can participate in the straw vote. The Candidate Technologies will be ordered according to which received the largest number of votes. Consensus approval will be our goal, but a 75% affirmative vote will be required as a minimum. This is what is meant by the term approximate consensus. REDO THIS SLIDE

  31. 9:20 Review Process for selecting beyond CMOS emerging technologies 9:45 Discuss Technologies 9:45 NEMS Switch Technology 10:05 Spin Torque Transfer Technology 10:25 Carbon-based Nanoelectronics 10:45 Break 11:00 Atomic Switch / Electrochemical Metal Switch 11:20 Collective Spin Devices (including M-QCA) 11:40 Single Electron Transistors 12:00 CMOL and FPNI ERD “Beyond CMOS” Technology Selection MtgAgenda – SECOND DAY REDO THIS SLIDE

  32. 12:50 Preliminary vote on technologies – Majority voting process 1:00 Discuss preliminary results 1:45 Second vote on technologies 2:00 Discuss the leading technologies resulting from vote 2:30 Final vote on the leading technology(ies) to determine if we have approximate consensus (75% of those voting) to recommend one or more for roadmapping and enhanced engineering development 2:45 Decide next steps in roadmapping the chosen technologies ERD “Beyond CMOS” Technology Selection Mtg Agenda – SECOND DAY (Cont’d) REDO THIS SLIDE

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